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Author SHA1 Message Date
Boris Brezillon
f21c163baa panvk: Clean Midgard leftovers in the cmd_close_batch() path 
pan_preload_fb() will use pre-frames on Bifrost. Pass NULL preload_jobs
and assert that num_preload_jobs is zero.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29382>
 2024-05-28 16:03:30 +00:00
Erik Faye-Lund
dd8fb7139d mesa/main: rewrite mipmap generation code 
The old mipmap generation code has a few problems:

1. It open-codes the format conversion, which is error prone, and it's
   hard to know if we're missing some formats. Manual inspection shows
   that we're indeed missing some less commonly used formats.

2. When downsampling between two miplevels with the same width (e.g a
   width of one), the code would read from outside the image.

3. It averages sRGB textures in gamma space. Whilte that's legal in GL
   (the filtering algorithm is undefined), it doesn't produce very good
   results. And it's not the same thing as util_gen_mipmap() does.

4. Similarly, it uses a box-filter for the stencil values. And while
   that's actually what the spec recomments (regardless of format), it's
   absolutely *not* what most applications would want. Using nearest
   sampling would make more sense.

5. It has requirements about the type and format returned by
   _mesa_uncompressed_format_to_type_and_comps() which other call-sites
   in mesa doesn't have. This is the real reason I want to get rid of
   it, because it ends up complicating the GLES read formats / types.

So, let's rewrite all of this, fixing all of the above. The result is
quite a bit shorter, and if this ends up being less performant, it's
unlikely that this matters, because we almost always use the GPU
accelerated code-path provided by util_gen_mipmap() anyway.

The new code works by a few identities: It uses the pack / unpack
helpers to convert the texture to a few reasonable intermediate formats,
so we keep the amount of open-coded averaging to a minimum. To do this
without heap-allocations, we introduce a concept of a "span", which has
a max fixed size, that can trivially be allocated on the stack.

We also add some more requirements to keep things sane; the higher level
do_row functions only allow the dest image to be half of the source
width or one (whichever is larger). This matches the high-level needs of
mipmap generation. The lower level do_span() function is a bit more
flexible, because that turns out to be helpful when implementing
do_span_3D(), where we want to avoid collapsing the inner dimension
twice.

Tested-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29380>
 2024-05-28 15:04:14 +00:00
Erik Faye-Lund
cd37384985 util/format: correct a typo 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29380>
 2024-05-28 15:04:14 +00:00
Rohan Garg
6fc6f95e90 intel/genxml: Update STATE_COMPUTE_MODE for Xe2 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg
f5a5c35717 intel/genxml: update MI_SEMAPHORE_WAIT for Xe2 
Rework:
 * José: Restore "Register Poll Mode" default to "Memory Poll"
 * José: Other minor formatting changes to match other genxml

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg
569a037fb1 intel/genxml: Update XY_BLOCK_COPY_BLT 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg
26e78f83bb intel/genxml: update CFE_STATE for LNL 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg
7001134246 isl: enable compression for CPS buffers on xe2+ 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg
b9c68883c4 intel/genxml: update 3DSTATE_CPSIZE_CONTROL_BUFFER for xe2+ 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Rohan Garg
bd09649750 intel/genxml: add the new state byte stride instruction 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Jordan Justen
17b6db893b intel/genxml: Update 3DSTATE_BTD for xe2 
Reworks:
  - Rohan: 3DSTATE_BTD can also be emitted on the CCS

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Jordan Justen
5709bbe033 intel/genxml: Add XY_FAST_COLOR_BLT for xe2 
Reworks:
  - Rohan: Use a uint for the surface format since we're dropping the
    SURFACE_FORMAT enum from genxml

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Jordan Justen
92fa87f5bd blorp: Update programming for XY_FAST_COLOR_BLT on xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29264>
 2024-05-28 14:42:19 +00:00
Samuel Pitoiset
7605456a9b radv: apply the SQ_THREAD_TRACE_WPTR workaround on GFX11 only 
GFX12 doesn't seem affected according to RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29426>
 2024-05-28 13:59:31 +00:00
Samuel Pitoiset
33ae2275bf radv: apply the workaround for no PS inpputs and LDS on GFX11 only 
GFX12 doesn't seem affected according to RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29426>
 2024-05-28 13:59:31 +00:00
Konstantin Seurer
a93f95c69c radv/rt: Remove load_rt_dynamic_callable_stack_base_amd 
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28619>
 2024-05-28 12:23:45 +00:00
Konstantin Seurer
432f3eb9ca radv/rt: Track ray_launch_size reads 
Totals from 33 (8.71% of 379) affected shaders:
Instrs: 1434025 -> 1433988 (-0.00%); split: -0.01%, +0.00%
CodeSize: 7578824 -> 7578472 (-0.00%); split: -0.01%, +0.00%
Latency: 9241632 -> 9241639 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 3407014 -> 3407049 (+0.00%); split: -0.00%, +0.00%
VClause: 40399 -> 40391 (-0.02%)
SClause: 37755 -> 37760 (+0.01%); split: -0.04%, +0.05%
Copies: 169588 -> 169567 (-0.01%); split: -0.04%, +0.02%
PreSGPRs: 4323 -> 4319 (-0.09%)
VALU: 940500 -> 940484 (-0.00%); split: -0.00%, +0.00%
SALU: 220508 -> 220509 (+0.00%); split: -0.03%, +0.03%

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28619>
 2024-05-28 12:23:45 +00:00
Konstantin Seurer
7ba8fccad3 radv/rt: Track ray_launch_id reads 
We can expect the z-component to be unused most of the times. Avoid
preserving it in those cases.

Totals from 94 (24.80% of 379) affected shaders:
MaxWaves: 916 -> 935 (+2.07%)
Instrs: 3316697 -> 3318357 (+0.05%); split: -0.06%, +0.11%
CodeSize: 17618704 -> 17616680 (-0.01%); split: -0.09%, +0.08%
VGPRs: 11632 -> 11520 (-0.96%)
SpillSGPRs: 1139 -> 1205 (+5.79%); split: -0.35%, +6.15%
Latency: 22595907 -> 22598225 (+0.01%); split: -0.15%, +0.16%
InvThroughput: 7036479 -> 6923740 (-1.60%); split: -1.74%, +0.14%
VClause: 104325 -> 104361 (+0.03%); split: -0.16%, +0.19%
SClause: 83920 -> 83925 (+0.01%); split: -0.08%, +0.08%
Copies: 328140 -> 330687 (+0.78%); split: -0.27%, +1.05%
Branches: 134521 -> 134541 (+0.01%); split: -0.01%, +0.02%
PreSGPRs: 8753 -> 8806 (+0.61%)
PreVGPRs: 10984 -> 10937 (-0.43%)
VALU: 2149880 -> 2151318 (+0.07%); split: -0.08%, +0.15%
SALU: 499107 -> 499128 (+0.00%); split: -0.08%, +0.09%

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28619>
 2024-05-28 12:23:45 +00:00
Konstantin Seurer
9fe34a3204 radv: Remove uses_dynamic_rt_callable_stack 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28619>
 2024-05-28 12:23:45 +00:00
Konstantin Seurer
1038f48dd1 radv: Replace is_rt_shader with RADV_SHADER_TYPE_RT_PROLOG 
The flag was only used for identifying the rt prolog.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28619>
 2024-05-28 12:23:45 +00:00
Eric R. Smith
272dcaff01 panfrost: fix some omissions in valhall flow control 
The code for checking flow control did not realize that
`LD_TEX` and `LD_TEX_IMM` were memory accesses, and hence was
not inserting waits where these were necessary. This showed up
as flakes in KHR-GLES31.core.shader_image_load_store.basic-glsl-misc-fs

Cc: mesa-stable
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29363>
 2024-05-28 11:18:14 +00:00
Rhys Perry
de07fd384d aco/gfx12: disallow SCC and most constants for BUF SOFFSET 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29330>
 2024-05-28 10:52:11 +00:00
Rhys Perry
12b4bdc134 aco/gfx12: decrease max_nsa_vgprs for VSAMPLE 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29330>
 2024-05-28 10:52:11 +00:00
Rhys Perry
b1b3237590 aco/gfx12: remove MIMG vector affinity 
Since GFX12 uses NSA unconditionally, there is no code size advantage to
avoiding it.

fossil-db (gfx1200):
Totals from 41700 (52.52% of 79395) affected shaders:
MaxWaves: 1063633 -> 1063623 (-0.00%); split: +0.00%, -0.00%
Instrs: 32745913 -> 32736332 (-0.03%); split: -0.10%, +0.07%
CodeSize: 177664256 -> 177623280 (-0.02%); split: -0.08%, +0.06%
VGPRs: 1668640 -> 1665280 (-0.20%); split: -0.26%, +0.06%
Latency: 248630176 -> 248803989 (+0.07%); split: -0.23%, +0.30%
InvThroughput: 51923793 -> 51958560 (+0.07%); split: -0.15%, +0.22%
VClause: 633381 -> 633594 (+0.03%); split: -0.31%, +0.34%
SClause: 1090207 -> 1090206 (-0.00%); split: -0.02%, +0.02%
Copies: 2042437 -> 2040188 (-0.11%); split: -0.53%, +0.42%
Branches: 680437 -> 680416 (-0.00%); split: -0.01%, +0.01%
VALU: 19387160 -> 19384917 (-0.01%); split: -0.06%, +0.04%
SALU: 3112590 -> 3112540 (-0.00%); split: -0.01%, +0.00%
VOPD: 5474 -> 5527 (+0.97%); split: +2.87%, -1.90%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29330>
 2024-05-28 10:52:11 +00:00
Rhys Perry
8bc03668e1 radv/gfx12: don't add workgroup id shader args 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29330>
 2024-05-28 10:52:11 +00:00
Rhys Perry
ef74407577 aco/gfx12: use ttmp9/ttmp7 for workgroup id 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29330>
 2024-05-28 10:52:11 +00:00
Rhys Perry
c8123b67e0 aco/gfx12: don't create v_fmac_legacy_f32 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29330>
 2024-05-28 10:52:11 +00:00
Rhys Perry
e79a8219d2 aco/gfx12: sign-extend s_getpc_b64 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29330>
 2024-05-28 10:52:11 +00:00
Rhys Perry
ae18c88409 aco/gfx12: implement workgroup barrier 
Same sequence LLVM uses for llvm.amdgcn.s.barrier.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29330>
 2024-05-28 10:52:11 +00:00
Rhys Perry
fae2a85d57 aco/gfx12: implement subgroup shader clock 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29330>
 2024-05-28 10:52:11 +00:00
Rhys Perry
872dda2bc5 aco: support GFX12 in insert_NOPs 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29330>
 2024-05-28 10:52:11 +00:00
Jose Maria Casanova Crespo
4835dc0e7f v3dv: Emit stencil draw clear if needed for GFXH-1461 
Fixes: 1e81bb05ae (v3dv: implement workaround for GFXH-1461)
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29427>
 2024-05-28 10:29:18 +00:00
Iago Toral Quiroga
9912c734e9 v3dv: implement vkCmdBindIndexBuffer2KHR 
This is added with VK_KHR_maintenance5. It adds a size parameter
to track the size of the index buffer data bound.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29425>
 2024-05-28 11:37:47 +02:00
Iago Toral Quiroga
e00da33474 v3dv: use pSizes paramater in vkCmdBindVertexBuffers2 
We can use this to specify the maximum vertex index that can
be accessed, which the hardware will use to detect and prevent
out-of-bounds accesses to vertex buffers.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29425>
 2024-05-28 11:37:42 +02:00
Iago Toral Quiroga
70aa470bdb v3dv: fix incorrect index buffer size 
When programming the size, we should take into account the
offset from the start of the index buffer address.

cc: mesa-stable

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29425>
 2024-05-28 11:37:37 +02:00
Iago Toral Quiroga
6d2edd2585 v3dv: drop unused stride field from v3dv_pipeline_vertex_binding 
This is unused since f4d426fae6 where we added support for dynamic
state vertex strides.

Fixes: f4d426fae6 ('v3dv: provide implementation for vkCmdBindVertexBuffers2')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29425>
 2024-05-28 11:37:19 +02:00
Samuel Pitoiset
a9f4931a91 ac,radv,radeonsi: a function that sets mutable CB surface fields 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29378>
 2024-05-28 08:49:53 +00:00
Tapani Pälli
6836118cd2 anv/android: enable emulated astc for applications 
This layer was blocking Android emulated ASTC support as it did not
take "emu_astc_ldr" in to account.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Mi, Yanfeng <yanfeng.mi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29415>
 2024-05-28 08:11:49 +00:00
Konstantin Seurer
28be0cca45 radv: Add locking to radv_replay_shader_arena_block 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29169>
 2024-05-28 07:11:02 +00:00
Konstantin Seurer
c31038ef98 llvmpipe: Use a second LLVMContext for compiling sample functions 
LLVMContextr is not thread safe. There are many code paths that use
llvmpipe_context::context and adding locking to all of them is
difficult and adds unnecessary overhead. This approach restricts locking
to lp_sampler_matrix, which makes covering all uses of the LLVMContext
easy and only adds overhead when running lavapipe.

Fixes: 7ebf7f4 ("llvmpipe: Compile sample functioins on demand")
Reviewed-by: Roland Scheidegger <roland.scheidegger@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29397>
 2024-05-28 06:30:58 +00:00
Iago Toral Quiroga
a93b1960af v3dv: emit a default point size when drawing points 
Before VK_KHR_maintenance5 point size is undefined unless the
shader explicitly writes it, but this extension changes this and
expects a default point size of 1.0 if none has been written.

We accomplish this by emitting a POINT_SIZE packet with the
default point size the first time we draw with a POINT primitive
in the job. If the shaders used in the draw call doesn't write
point size then the hardware will take the point size from the
state set by the packet. If the shader does write to point size
then the value written in the shader will be used instead.

Passes all tests we support in:
dEQP-VK.rasterization.primitive_size.default_size.points.*
when forcing maintenance5 enabled.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29413>
 2024-05-28 05:31:13 +00:00
Iago Toral Quiroga
7e0616ecc5 v3dv: only flag 'shader writes point size' if the shader actually writes it 
If the shader writes point size, then the compiler needs to ensure it
writes it in the appropriate vpm output slot and also clamp its value to
expected limits. This is why we have the per_vertex_point_size in the
shader key, so it doesn't really make sense to set this if the shader
doesn't write point size.

If the shader record flags that the shader writes point size then the
hardware will use the shader written value to override point size state
(set with the POINT_SIZE packet), so again, we really only want to set
this in the shader state record if the shader actually writes its value.

While we could also limit this to point primitives, since these are the
only primitives where point size has an effect, this is not really
required, and skipping this allows us to use the same shader with any
primitive type (otherwise we would have to compile 2 different shaders).

Finally, this change makes the vertex shader setup for point size match the
one we had been doing for geometry shaders, so it makes both stages behave
consistently regarding point size behavior.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29413>
 2024-05-28 05:31:13 +00:00
Iago Toral Quiroga
c30833f233 broadcom/compiler: check if vertex shader writes point size 
The same we already check for geometry shaders. We will use this
shortly.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29413>
 2024-05-28 05:31:13 +00:00
Karol Herbst
7c07f1cdfb nouveau: import nvif/ioctl.h file from libdrm_nouveau 
Technically this is UAPI and should be moved into the UAPI headers, but
for now let's unbreak users this way.

Fixes: 821f4c8d99 ("nouveau: import libdrm_nouveau")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29420>
 2024-05-27 22:23:41 +00:00
Konstantin Seurer
9b932aadf4 radv: Remove radv_cmd_dirty_dynamic_bits 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29345>
 2024-05-27 20:34:36 +00:00
Sergi Blanch Torne
d963fd596e ci: fix stress counter in run'n'monitor 
The stress counter after enable_job(retry), often stores the new status
instead of the job complete. So, the summary printed later doesn't show the
real evolution of the test.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29416>
 2024-05-27 20:30:36 +00:00
José Roberto de Souza
a47c5c9eee intel/perf: Add intel_perf_stream_read_samples() 
Because of the differences between i915 and Xe KMD this function is
needed to abstract the special handling that Xe KMD needs while
reading perf stream.
This special handling will be implemented in the next patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29421>
 2024-05-27 19:34:06 +00:00
José Roberto de Souza
9841aeb6ad intel/perf: Add a macro with header + sample length 
To be more explicit lets have 2 macros one with sample lenght other
with header and sample length.

This will also help add Xe KMD support as it don't have a header like
i915.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29421>
 2024-05-27 19:34:06 +00:00
José Roberto de Souza
2f128b2ba5 intel/perf: Replace drm_i915_perf_record_header by intel_perf_record_header 
drm_i915_perf_record_header requires i915_drm.h but we want to remove
all i915_drm.h includes from common code, so replacing it by
intel_perf_record_header.

No changes in behavior expected as the structs and enums are identical.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29421>
 2024-05-27 19:34:06 +00:00
José Roberto de Souza
da43bf3f2e intel/perf: Allocate sseu in heap memory 
This is a i915 specific struct and Xe KMD will not need anything like
that so lets allocate it in heap memory.
This will help us remove the i915_drm.h includes from common code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29421>
 2024-05-27 19:34:06 +00:00