Commit Graph

50709 Commits

Author SHA1 Message Date
Jordan Justen
f16b39f05c state_tracker: set PrimitiveRestartInSoftware if needed
If the PIPE_CAP_PRIMITIVE_RESTART screen param is not set, then enable
PrimitiveRestartInSoftware to enable software primitive restart
support in the VBO module.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-05-17 10:54:26 -07:00
Jordan Justen
862667b6d9 vbo: use software primitive restart in the VBO module
When PrimitiveRestartInSoftware is set, the VBO module will handle
primitive restart scenarios before calling the vbo->draw_prims
drawing function.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-05-17 10:54:26 -07:00
Jordan Justen
fc22fde9d8 mesa: add PrimitiveRestartInSoftware to gl_context.Const
If set, then the VBO module will handle all primitive
restart scenarios before calling the driver draw_prims.

Software primitive restart support is disabled by default.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-05-17 10:54:26 -07:00
Jordan Justen
bc8e0f5b0f vbo: add software primitive restart support
vbo_sw_primitive_restart implements primitive restart in software
by splitting primitive draws apart.

This is based on similar support in mesa/state_tracker/st_draw.c.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-05-17 10:54:26 -07:00
Eric Anholt
5a827d9a2b mesa: Check for framebuffer completeness before looking at the rb.
Otherwise, an incomplete framebuffer could have a NULL
_ColorReadBuffer and we'd deref that.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-05-17 10:05:24 -07:00
Eric Anholt
8b7ba92605 mesa: Fix assertion failure when a cube face is not present.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-05-17 10:05:24 -07:00
Eric Anholt
aa5ec13775 glsl: Drop the extra NULL specifiction on ir_assignment constructors.
It's an implied argument, and I don't think being explicit about it
helps.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-05-17 10:05:24 -07:00
Eric Anholt
9c4e9ce051 glsl: Fix assertion failure on handling switch on uint expressions.
Fixes piglit glsl-1.30/execution/switch/fs-uint.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-05-17 10:05:24 -07:00
Eric Anholt
bbbc7c7d56 glsl: Reject non-scalar switch expressions.
The comment quotes spec saying that only scalar integers are allowed,
but we only checked for integer.

Fixes piglit switch-expression-const-ivec2.vert

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-05-17 10:05:24 -07:00
Eric Anholt
5d6ea16dfe glsl: Let the constructor figure out the types of switch-related expressions.
I noticed this while unindenting the code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-05-17 10:05:24 -07:00
Eric Anholt
5462f3679a glsl: Fix indentation of switch code.
I managed to completely trash it in 22d81f15.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-05-17 10:05:23 -07:00
Eric Anholt
aa02884c4f i965/vs: Fix up swizzle for dereference_array of matrices.
Fixes assertion failure in piglit:
vs-mat2-struct-assignment.shader_test
vs-mat2-array-assignment.shader_test

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-05-17 10:05:23 -07:00
Eric Anholt
ef691885c9 mesa: Throw error on glGetActiveUniform inside Begin/End.
Fixes piglit GL_ARB_shader_objeccts/getactiveuniform-beginend.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-05-17 10:05:23 -07:00
Eric Anholt
05c200bac0 glsl: Improve the local dead code optimization to eliminate unused channels.
Total instructions: 261582 -> 261316
135/2147 programs affected (6.3%)
36752 -> 36486 instructions in affected programs (0.7% reduction)

This excludes a tropics shader that now gets 16-wide mode and throws
off the numbers.  5 shaders are hurt: two extra MOVs in 4 tropics
shaders it looks like because we don't split register names according
to independent webs, and one gstreamer shader where it looks like
try_rewrite_rhs_to_dst() is falling on its face.

This should also help avoid a regression in VSes from idr's ARB
programs to GLSL work.
2012-05-17 10:05:23 -07:00
Eric Anholt
f220f73b9c i965/fs: Do more register coalescing by using the interference graph.
By using the live variables code for determining interference, we can
handle coalescing in the presence of control flow, which the other
register coalescing path couldn't.

Total instructions: 207184 -> 206990
74/1246 programs affected (5.9%)
33993 -> 33799 instructions in affected programs (0.6% reduction)

There is a newerth shader that loses out, because of some extra MOVs
that now get their dead-code nature obscured by coalescing.  This
should be fixed by doing better at dead code elimination.
2012-05-17 10:05:23 -07:00
Christoph Bumiller
1befacc764 nouveau: place static buffers in VRAM if preferred by the driver 2012-05-17 15:24:58 +02:00
Christoph Bumiller
717f55d79d nv50/ir: fix reversed order of lane ops in quadops 2012-05-17 15:24:58 +02:00
Christoph Bumiller
e6caafd9d7 nv50,nvc0: handle user vertex buffers
And restructure VBO validation a little in the process.
2012-05-17 15:24:58 +02:00
Christoph Bumiller
ef7bb28129 nv50,nvc0: handle user index buffers 2012-05-17 15:24:58 +02:00
Christoph Bumiller
fcb2868210 nv50,nvc0: handle user constbufs without wrapping them in a resource 2012-05-17 15:24:58 +02:00
Christoph Bumiller
07323a80a2 st/mesa: set PIPE_BIND_STREAM_OUTPUT for TFB target in st_bufferobj_data 2012-05-17 15:24:58 +02:00
Jeremy Huddleston
d65bd195ec darwin: Eliminate a possible race condition while destroying a surface
Introduced by: c60ffd2840
Signed-off-by: Jeremy Huddleston <jeremyhu@apple.com>
2012-05-16 18:58:30 -07:00
Jeremy Huddleston
a73a800b32 darwin: Unlock our mutex before destroying it
http://xquartz.macosforge.org/trac/ticket/575

Signed-off-by: Jeremy Huddleston <jeremyhu@apple.com>
2012-05-16 18:58:29 -07:00
Michel Dänzer
7446a0407d gallium/radeon: Fix r300g tiling breakage.
Commit 11f056a3f0 broke the r300g build. Fix it
up, and reinstate some code which isn't needed by r600g and radeonsi but is
by r300g.
2012-05-16 23:52:19 +02:00
Francisco Jerez
03e3bc4ba5 gallium/auxiliary/pipe-loader: Fix usage of anonymous union.
Anonymous unions aren't part of the C99 standard.  Fixes build on GCC
versions older than 4.6.

https://bugs.freedesktop.org/show_bug.cgi?id=50001

Reported-by: Michael Lange <michaell@gmx.org>
2012-05-16 18:51:35 +02:00
Michel Dänzer
88a2e2388b radeonsi: Initial tiling support.
Largely based on the corresponding Evergreen support in r600g.
2012-05-16 18:30:50 +02:00
Michel Dänzer
11f056a3f0 r600g: Set tiling information for BOs being shared.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=48747
2012-05-16 18:30:45 +02:00
Michel Dänzer
76d6a64de3 st/xorg: Better handling of EXA copies.
Always use the resource_copy_region hook. If a source and destination rectangle
overlap, copy to/from a temporary pixmap.
2012-05-16 18:30:39 +02:00
Michel Dänzer
0201c7d0af radeonsi: Bump MAX_DRAW_CS_DWORDS.
I missed this when updating si_context_draw().
2012-05-16 18:30:07 +02:00
José Fonseca
9af1ba565d draw,llvmpipe: Avoid named struct types on LLVM 3.0 and later.
Starting with LLVM 3.0, named structures are meant not for debugging, but
for recursive data types, previously also known as opaque types.

The recursive nature of these types leads to several memory management
difficulties.  Given that we don't actually need recursive types, avoid
them altogether.

This is an attempt to address fdo bugs 41791 and 44466. The issue is
somewhat random so there's no easy way to check how effective this is.
2012-05-16 15:00:23 +01:00
Olivier Galibert
982df3c1a5 llvmpipe: Color slot interpolation can be flat or perspective, not linear.
Fixes a bunch of glsl 1.10 interpolation piglit tests.

Signed-off-by: Olivier Galibert <galibert@pobox.com>
Signed-off-by: José Fonseca <jfonseca@vmware.com>
2012-05-16 13:12:04 +01:00
Homer Hsing
4050756804 configure.ac: Fix typos in the r600-llvm-compiler option
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
2012-05-15 19:02:27 -04:00
José Fonseca
563489e5c9 gallivm: Add MCRegisterInfo.h to silence benign warnings about missing implementation.
Trivial.
2012-05-15 23:48:24 +01:00
Paul Berry
6335e0b073 i965/blorp: Move exec() out of brw_blorp_params.
No functional change.  This patch replaces the
brw_blorp_params::exec() method with a global function
brw_blorp_exec() that performs the operation described by the params
data structure.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-05-15 15:15:26 -07:00
Paul Berry
19e9b24626 i965/gen6: Initial implementation of MSAA.
This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to
understand multisampled buffers, adapting the rendering pipeline setup
to enable multisampled rendering, and adding multisample resolve
operations to brw_blorp_blit.cpp. Some preparation work is also
included for Gen7, but it is not yet enabled.

MSAA support is still fairly preliminary.  In particular, the
following are not yet supported:
- Fully general blits between MSAA and non-MSAA buffers.
- Formats other than RGBA8, DEPTH24, and STENCIL8.
- Centroid interpolation.
- Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE,
  GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE,
  GL_SAMPLE_COVERAGE_INVERT).

Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on
i965/Gen6.

v2:
- In intel_alloc_renderbuffer_storage(), quantize the requested number
  of samples to the next higher sample count supported by the
  hardware.  This ensures that a query of GL_SAMPLES will return the
  correct value.  It also ensures that MSAA is fully disabled on Gen7
  for now (since Gen7 MSAA support doesn't work yet).
- When reading from a non-MSAA surface, ensure that s_is_zero is true
  so that we won't try to read from a nonexistent sample.
2012-05-15 15:09:23 -07:00
Paul Berry
506d70be21 i965/gen6+: Add code to perform blits on the render path ("blorp").
This patch expands the "blorp" component to be able to perform blits
as well as HiZ resolves.  The new blitting code is located in
brw_blorp_blit.cpp.  This includes the necessary fragment shader code
to look up pixels in the source buffer (which is configured as a
texture) and output them to the destination buffer (which is
configured as the render target).

Most of the time the fragment shader code is simple and
straightforward, since it merely has to apply a coordinate offset,
read from the texture, and write to the render target.  However, in
the case of blitting stencil buffers, things are more complicated,
since the GPU stores stencil data using W tiling, and W tiling is not
supported for textures or render targets.  So, we set up the stencil
buffers as Y tiled, and emit fragment shader code that adjusts the
coordinates to account for the difference between W and Y tiling.
Furthermore, since a rectangular region in W tiling does not
necessarily correspond to a rectangular region in Y tiling, we widen
the rectangle primitive to the nearest tile boundary and have the
fragment shader "kill" any pixels that don't fall inside the actual
desired destination rectangle.

All of this is a necessary prerequisite for implementing MSAA, since
we'll need to be able to blit between multisample color, depth, and
stencil buffers and their non-multisampled counterparts, and none of
the existing blitting mechanisms support multisampling.

In addition, the new blitting code should speed up operations where we
previously fell back to software rasterization, such as blitting of
stencil buffers.  The current fallback sequence is: first we try to do
a blit using the hardware blitting engine.  If that fails we try to do
a blit using the render path.  If that also fails then we do the blit
using a meta-op (which may or may not fall back to software
rasterization).

Note that blitting using the render path has some limitations at the
moment: it only supports a few formats, and it doesn't support
clipping or scissoring.  These limitations will be addressed in future
patch series.

v2:
- Add the code that configures the WM program to
  gen{6,7}_emit_wm_config() and gen7_emit_ps_config() rather than
  creating separate ...enable() functions.
- Call intel_prepare_render before determining which miptrees we are
  blitting from/to, because it may cause miptrees to be reallocated.
- Allow the blit to mirror X and/or Y coordinates.
- Disable blorp blits on Gen7 for now, since they aren't working yet.
2012-05-15 15:09:23 -07:00
Paul Berry
36e3413418 i965: Expose surface setup internals for use by blits.
This patch exposes the functions brw_get_surface_tiling_bits and
gen7_set_surface_tiling, so that they can be re-used when setting up
surface states in gen6_blorp.cpp and gen7_blorp.cpp.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-05-15 15:09:22 -07:00
Paul Berry
586b389474 i965: split gen{6,7}_blorp_exec functions into manageable chunks.
This patch splits up the gen6_blorp_exec and gen7_blorp_exec
functions, which were very long, into simple component functions.
With a few exceptions, there is one function per state packet.

This will allow blit functionality to be added without significantly
complicating the code.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>

v2: Rename the functions gen{6,7}_emit_wm_disable() to
gen{6,7}_emit_wm_config() (since the WM is not actually disabled
during HiZ ops; it simply doesn't have a program).  Also, on gen7,
split out the configration of 3DSTATE_PS to a separate function
gen7_emit_ps_config().
2012-05-15 15:09:22 -07:00
Paul Berry
2c5510b71b i965: Parameterize HiZ code to prepare for adding blitting.
This patch groups together the parameters used by the HiZ functions
into a new data structure, brw_hiz_resolve_params, rather than passing
each parameter individually between the HiZ functions.  This data
structure is a subclass of brw_blorp_params, which represents the
parameters of a general-purpose blit or resolve operation.  A future
patch will add another subclass for blits.

In addition, this patch generalizes the (width, height) parameters to
a full rect (x0, y0, x1, y1), since blitting operations will need to
be able to operate on arbitrary rectangles.  Also, it renames several
of the HiZ functions to reflect the expanded role they will serve.

v2: Rename brw_hiz_resolve_params to brw_hiz_op_params.  Move
gen{6,7}_blorp_exec() functions back into gen{6,7}_blorp.h.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-05-15 15:09:22 -07:00
Kenneth Graunke
610910a66d i965: Implement guardband clipping on Ivybridge.
Improves performance in Citybench:
- 320x240: 9.19589% +/- 0.557621%
- 1280x480: 3.90797% +/- 0.774429%

No apparent difference in OpenArena.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-05-15 14:52:24 -07:00
Kenneth Graunke
85cd30406f i965: Implement guardband clipping on Sandybridge.
Improves performance in Citybench:
- 320x240:  19.8008% +/- 0.937818%
- 1280x480: 6.53856% +/- 0.859083%

No apparent difference in OpenArena nor Xonotic.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-05-15 14:52:24 -07:00
José Fonseca
5994a641d8 llvmpipe: Add a test for lp_build_sgn.
Only floating point though, but better than nothing.
2012-05-15 22:39:25 +01:00
José Fonseca
9fb4eef6a1 gallivm: Fix lp_build_sgn for normalized/fixed-point integers.
These types got broken with the recent commit that fixed lp_build_sgn
for negative integers.
2012-05-15 22:39:24 +01:00
José Fonseca
c95cea50a9 gallivm: Fix lp_build_const_xxx for negative integers.
Do proper rounding.

Thanks to Olivier Galibert for investigating this.
2012-05-15 22:39:24 +01:00
Brian Paul
1459c18f45 svga: fix FBO / viewport bugs
When drawing to a FBO, the viewport wasn't always set correctly.  It
was fine in the usual case of the viewport dims matching the surface
dims but broken otherwise.  In particular, this was happening because
the viewport scale is negative for FBO rendering.

The piglit fbo-viewport test exercises this.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
2012-05-15 14:56:54 -06:00
Vadim Girlin
4a8d47c264 radeon/llvm: add support for texture offsets, fix TEX_LD
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-05-15 18:53:20 +04:00
Vadim Girlin
fa5a963dd6 radeon/llvm: add SET_GRADIENTS*, fix SAMPLE_G
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-05-15 18:53:06 +04:00
Vadim Girlin
b655f78b25 radeon/llvm: increase const regs count
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-05-15 18:48:26 +04:00
Vadim Girlin
12a2374da3 radeon/llvm: use IntrNoMem property for intrinsics where possible
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-05-15 18:48:16 +04:00
Vadim Girlin
63a8595271 radeon/llvm: use correct intrinsic for CEIL
Should be round_posinf instead of round_neginf.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-05-15 18:48:06 +04:00