Commit Graph

98962 Commits

Author SHA1 Message Date
Neil Roberts
0bd1c4676d mesa: Add GL4.6 aliases of functions from GL_ARB_indirect_parameters
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-01-05 11:41:10 +01:00
Samuel Pitoiset
ec63ab39be radv: enable denorms for 64-bit and 16-bit floats
Similar to RadeonSI.

This fixes:
dEQP-VK.image.texel_view_compatible.graphic.basic.attachment_read.bc*r16g16b16a16_sfloat
dEQP-VK.image.extended_usage_bit.attachment_write.r16_sfloat

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-05 09:51:33 +01:00
Samuel Pitoiset
7643c71527 amd/common: correctly detect if we need ring buffers
When allocate_user_sgprs() was called, ctx->stage was actually
unset and 0 is for the vertex shader. This doesn't change
anything for now because of the spill support thing.

Though, the number of user SGPRs has to be fixed for merged
shaders on GFX9. It was broken before anyway.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-05 09:49:51 +01:00
Samuel Pitoiset
50cfad0298 amd/common: use ac_image_load when lod is zero
This might decrease VGPR spilling, because we no longer
have to use v4i32 for 2D fetches when level == 0. We now
use v2i32 for those cases.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 09:49:45 +01:00
Samuel Pitoiset
85769759bf radv: limit the scissor bug workaround to Vega 10 and Raven
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-05 09:47:49 +01:00
Alejandro Piñeiro
2719467eb6 glsl/standalone: set MaxTransformFeedbackBuffers
Using 4, as it is the default value on mesa. See mesa/main/config.h
and the following commit that introduced the value:
15ac66e331

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-01-05 08:52:22 +01:00
Alejandro Piñeiro
0ba3de2ad7 glsl/standalone: set MaxVertexStreams
ARB_transform_feedback3 sets a minimum of 1, ARB_gpu_shader5 a minimum
of 4. It shouldn't matter too much, so choosing the later.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-01-05 08:52:22 +01:00
Alejandro Piñeiro
8dcf131f04 glsl/standalone: set MaxUniformBufferBindings
Used to handle how many ubo you can define on the context. Minimimum
defined as 36 on ARB_uniform_buffer_object spec, up to 84 on OpenGL
4.6 (12 per stage at each moment).

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-01-05 08:52:22 +01:00
Alejandro Piñeiro
937b210551 glsl/standalone: point which arguments are mandatory
Every now and then I execute the standalone compiler, get the
non-version error, and need to remember what I'm doing wrong

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-01-05 08:52:22 +01:00
Timothy Arceri
4a0c24f2dd ac: rework ac_llvm_extract_elem()
Simplifies the logic a little and asserts index is 0.

Suggested-by: Nicolai Hähnle <nhaehnle@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 12:20:38 +11:00
Timothy Arceri
71f82dc9a3 st/glsl_to_nir/radeonsi: enable tessellation shaders
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
9755eeb15a gallium/tgsi: add patch support to tgsi_get_gl_varying_semantic()
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
452586b56a radeonsi: add dummy implementation of si_nir_scan_tess_ctrl()
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
14adf7853a ac/radeonsi: add load_tess_coord() to the abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
eb1e555cfd radeonsi: make si_llvm_emit_tcs_epilogue compatible with emit_outputs abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
91f3c4ec1b radeonsi/nir: gather tess properties
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
9e1a3caf32 ac/radeonsi: add tcs_rel_ids to the abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
9c2f877830 radeonsi: add unpack_llvm_param() helper
This allows us to pass the llvm param directly rather than looking
it up.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
f93740efc1 ac: add {tcs,tes}_patch_id to the abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
15c6f3fdd5 radeonsi: add nir support for tcs outputs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
b99ebaa4fd ac: move some helpers to ac_llvm_build.c
We will call these from the radeonsi NIR backend.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
2deb822075 ac: add store_tcs_outputs() to the abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
8be0135082 radeonsi: add si_nir_load_input_tcs()
V2: drop type param and just use ctx->i32

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
234507b3cf radeonsi: add get_dw_address_from_generic_indices() helper
This will be used by both the tgsi and nir backends.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
b104e7e172 ac: call load_tcs_input() via the abi
This also enables some code sharing with tes.

V2: drop type param and just use ctx->i32

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
b09a3196e0 ac: add load_tes_inputs() to the abi
V2: drop type param and just use ctx->i32

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Timothy Arceri
e04bf8a619 radeonsi: add si_nir_load_input_tes()
V2: drop type param and just use ctx->i32

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-05 11:58:55 +11:00
Tim Rowley
396c006d90 swr/rast: fix invalid sign masks in avx512 simdlib code
Should be 0x80000000 instead of 0x8000000.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-04 13:35:17 -06:00
Bas Nieuwenhuizen
76daa30e4a radv: Use correct flush bits for flushing L2 during CB/DB flushes.
Copied from radeonsi.

Putting in the correct metadata flush commands for eventually not
flushing L2 on CB/DB switch.

Does not remove the need for V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
at the moment.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-04 19:35:36 +01:00
Bas Nieuwenhuizen
f2c9f13ec2 radv: Invalidate L1 for VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT.
These are just shaders reads, so we need to invalidate L1.

Fixes: 6dbb0eaccc "radv: handle subpass cache flushes"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-04 19:35:36 +01:00
Samuel Pitoiset
2670ebb584 radv/gfx9: reduce the number of input VGPRs for the GS stage
This can still be improved, but let's start with this.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-04 18:43:25 +01:00
Samuel Pitoiset
a4d2782664 amd/common: scan if gl_PrimitiveID is used before translating to LLVM
It makes more sense to move all scan stuff in the same place.
Also, we don't really need to duplicate the uses_primid field
for each stages.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-04 18:43:09 +01:00
Samuel Pitoiset
3b2cb2f99a amd/common: scan if gl_InvocationID is used
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-04 18:43:07 +01:00
Rob Herring
aa187fe7bf egl/android: Fix build break with dri2_initialize_android _EGLDisplay parameter
Commit 2f421651ac ("egl: let each platform decided how to handle
LIBGL_ALWAYS_SOFTWARE") broke the build due to copy-n-paste of misnamed
function parameter.:

src/egl/drivers/dri2/platform_android.c:1183:8: error: use of undeclared identifier 'disp'

Rather than just fixing 'disp', rename the function parameter 'dpy' to
'disp' to align with the other EGL platforms' implementations.

Fixes: 2f421651ac ("egl: let each platform decided how to handle LIBGL_ALWAYS_SOFTWARE")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2018-01-04 10:18:10 -06:00
Alex Smith
00a81e9909 anv: Add missing unlock in anv_scratch_pool_alloc
Fixes hangs seen due to the lock not being released here.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-01-04 14:54:02 +00:00
Ilia Mirkin
e923075a82 mesa/bindless: fix missing image _Layer initialization
Some later code relies on _Layer to set first/last_layer. Make sure it's
always initialized.

Detected by valgrind's conditional jump/move with uninit value logic.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-04 02:22:25 -05:00
Józef Kucia
f222cf3c6d radeonsi: fix alpha-to-coverage if color writes are disabled
If alpha-to-coverage is enabled, we have to compute alpha
even if color writes are disabled.

Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-01-04 01:58:33 +01:00
Bas Nieuwenhuizen
79724c89f8 ac: rename has_sync_file to has_fence_to_handle.
sync_files are in linux since 4.7, while the amdgpu fence_to_handle
ioctl is only in 4.15.

In particular we don't need it for sync_file in radv, because
everything happens via syncobjs, which got support earlier than
fence_to_handle.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-01-04 01:12:09 +01:00
Bas Nieuwenhuizen
c99426ea83 ac/nir: Handle loading data from compact arrays.
Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-04 00:14:23 +01:00
Bas Nieuwenhuizen
1c78e4f053 radv: Allow writing 0 scissors.
When rasterization is disabled we can have that few.

Fixes: 76603aa90b "radv: Drop the default viewport when 0 viewports are given."
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-04 00:14:19 +01:00
Bas Nieuwenhuizen
5158603182 radv: Use correct HTILE expanded words.
Seems like users are actually hitting 0xFFFFFFFF actually making
things broken for them, and the mad max regression is fixed, so
lets put this in once more.

v2: Use 0xf for depth-only htile. (Dave)

Fixes: af2844116f "radv: Revert HTILE reset word to 0xFFFFFFFF."
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-04 00:14:03 +01:00
Marek Olšák
4f19cc82f9 ac: rename has_syncobj_wait -> has_syncobj_wait_for_submit
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-01-04 00:07:45 +01:00
Eric Anholt
81567d01c1 braodcom/vc5: Fix internal type/bpp for RGB10_A2UI images.
I found that we were getting GPU hangs on most tests rendering to them,
and the simulator was assertion failing.
2018-01-03 14:31:37 -08:00
Eric Anholt
a93fd7b41e broadcom/vc5: Try to fix up compressed texture load/store.
We were trying to load/store the logical width/height number of compressed
blocks.  As long as the textures were large, single-level, and the
load/store at (0,0), it kind of worked.
2018-01-03 14:31:36 -08:00
Eric Anholt
44237b3f85 broadcom/vc5: Fix image_h value for CPU-side tiling on miplevels > 1.
Fixes overflow that caused failure in
dEQP-GLES3.functional.texture.filtering.2d.sizes.128x128_linear.
2018-01-03 14:31:36 -08:00
Eric Anholt
e60e3a56a2 broadcom/vc5: Fix discard_if during control flow.
I want to do the SETMSF.IFA to discard only if execute == 0 and cond, so
our dest of the PUSHZ needs to be nonzero if execute or !cond are nonzero.

Fixes dEQP-GLES3.functional.shaders.discard.dynamic_loop_dynamic.
2018-01-03 14:31:36 -08:00
Eric Anholt
7836c85919 broadcom/vc5: Disable early Z when the stencil func isn't ALWAYS.
Apparently the other funcs will have observable differences when early Z
is enabled.

Fixes (new) simulator assertion failures in
dEQP-GLES3.functional.rasterizer_discard.basic.clear_depth.
2018-01-03 14:31:36 -08:00
Eric Anholt
635131a238 broadcom/vc5: Don't emit component 3/4 F16 TLB writes for float/vec2.
Fixes a simulator assertion failure on
dEQP-GLES3.functional.fragment_out.array.fixed.r8_highp_float.
2018-01-03 14:31:28 -08:00
Eric Anholt
deb552ca27 nir: Add a helper to get the uvec4 type.
I needed this in the vc5 compiler.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-01-03 14:25:23 -08:00
Eric Anholt
39811a2894 broadcom/vc5: Introduce enums for internal depth/type, with V3D prefixes. 2018-01-03 14:25:23 -08:00