Commit Graph

55600 Commits

Author SHA1 Message Date
Roland Scheidegger
4c12276607 llvmpipe: bump glsl version to 140
texel offsets should have been the last missing feature for 130, and in
fact 140 as well (last there were texture buffers). In any case we still
don't do OpenGL 3.0 (missing MSAA which will be difficult,
plus EXT_packed_float, ARB_depth_buffer_float and EXT_framebuffer_sRGB).

v2: bump to 140 instead - we have everything except we crash when not writing
to gl_Position (but softpipe crashes as well) so let's just say this is a bug
instead. Also (by Dave Airlie's suggestion) update llvm-todo.txt.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-03-02 02:54:30 +01:00
Roland Scheidegger
b3b3b389fa gallivm: add support for texel offsets for ordinary texturing.
This was previously only handled for texelFetch (much easier).
Depending on the wrap mode this works slightly differently (for somewhat
efficient implementation), hence have to do that separately in all roughly
137 places - it is easy if we use fixed point coords for wrapping, however
some wrapping modes are near impossible with fixed point (the repeat stuff)
hence we have to normalize the offsets if we can't do the wrapping in
unnormalized space (which is a division which is slow but should still be
much better than the alternative, which would be integer modulo for wrapping
which is just unusable). This should still give accurate results in all
cases that really matter, though it might be not quite conformant behavior
for some apis (but we have much worse problems there anyway even without
using offsets).
(Untested, no piglit test.)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-03-02 02:54:30 +01:00
Brian Paul
a99eb5c83f svga: always link with C++
Even when we don't have LLVM since there's other C++ code
in the resulting DRI driver object.

Note: This is a candidate for the stable branches.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-03-01 17:31:32 -07:00
Brian Paul
f6c0612618 st/mesa: convert ir_triop_lrp to TGSI_OPCODE_LRP
AFAICT, all gallium drivers implement TGSI_OPCODE_LRP.
Tested with softpipe, llvmpipe, svga drivers.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-03-01 17:31:32 -07:00
Chris Forbes
7616586cff docs: Mark some things done in GL3.txt 2013-03-02 12:02:25 +13:00
Martin Andersson
d96d8ed910 winsys/radeon: Only add bo to hash table when creating flink
The problem is that we mix bo handles and flinked names in the hash
table. Because kms type handles are not flinked they should not be
added to the hash table. If we do that we will sooner or later
get a situation where we will overwrite a correct entry because
the bo handle was the same as a flinked name.

Note: this is a candidate for the stable branches.

Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-03-01 17:52:40 -05:00
Chris Forbes
1d4dbeeaec i965: enable ARB_texture_multisample on Gen6+
V2: Works on Ivy Bridge now too, so this can be 6+.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-03-02 11:40:50 +13:00
Chris Forbes
26c8479474 i965/fs: add support for ir_txf_ms on Gen6+
On Gen6, lower this to `ld` with lod=0 and an extra sample_index
parameter.

On Gen7, use `ld2dms`. We don't support CMS yet for multisample
textures, so we just hardcode MCS=0. This is ignored for IMS and UMS
surfaces.

Note: If we do end up emitting specialized shaders based on the MSAA
layout, we can emit a slightly shorter message here in the UMS case.

Note: According to the PRM, `ld2dms` takes one more parameter, lod.
However, it's always zero, and including it would make the message too
long for SIMD16, so we just omit it.

V2: Reworked completely, added support for Gen7.
V3: - Introduce sample_index parameter rather than reusing lod
    - Removed spurious whitespace change
    - Clarify commit message
V4: - Fix comment style
    - Emit SHADER_OPCODE_TXF_MS on Gen6. This was benignly wrong since
      it lowers to `ld` anyway on this gen, but still wrong.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-03-02 11:40:50 +13:00
Chris Forbes
6883c8845d i965/vs: add support for ir_txf_ms on Gen6+
On Gen6, lower this to `ld` with lod=0 and an extra sample_index
parameter.

On Gen7, use `ld2dms`. This takes an additional MCS parameter to support
compressed multisample surfaces, but we're not enabling them for
multisample textures for now, so it's always ignored and can be safely
omitted.

V2: Reworked completely, added support for Gen7.
V3: - Use new sample_index, sample_index_type rather than reusing lod
    - Clarify commit message.
V4: - Fix comment style

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-03-02 11:40:49 +13:00
Chris Forbes
f52ce6a0ca i965: add a new virtual opcode: SHADER_OPCODE_TXF_MS
This is very similar to the TXF opcode, but lowers to `ld2dms` rather
than `ld` on Gen7.

V4: - add SHADER_OPCODE_TXF_MS to is_tex() functions, so regalloc thinks
      it actually writes the correct number of registers. Otherwise in
      nontrivial shaders some of the registers tend to get clobbered,
      producing bad results.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-03-02 11:40:49 +13:00
Chris Forbes
555dc6d74d i965: take the target into account for Gen7 MSAA modes
Gen7 has an erratum affecting the ld_mcs message, making it unsafe to
use when the surface doesn't have an associated MCS.

From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):

   "If this field is disabled and the sampling engine <ld_mcs>
   message is issued on this surface, the MCS surface may be
   accessed. Software must ensure that the surface is defined
   to avoid GTT errors."

To allow the shader to treat all surfaces uniformly, force UMS if the
surface is to be used as a multisample texture, even if CMS would have
been possible.

V3: - Quoted erratum text

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-03-02 11:39:42 +13:00
Chris Forbes
8cc26ae993 i965: Support multisampling in surface_state for textures
The surface_state setup for renderbuffers already worked; only the
texturing side needed work. BLORP does something similar, but does its
own surface_state setup.

On Gen6, we just need to set the correct sample count.

On Gen7: - set the correct sample count
         - set the correct layout mode
         - set GEN7_SURFACE_ARYSPC_LOD0 if it's set in the miptree.

V2: - Clarify commit message
    - Rebased onto Paul's physical/logical dims cleanup
    - Added Gen7 support

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-03-02 11:35:24 +13:00
Chris Forbes
e62b6a10bc i965: add support for multisample textures
V2: - Fix for state moving from texobj to image
    - Rebased onto Paul's logical/physical cleanup
    - Fixed missing quantization of sample count
    - Fold in IMS renderbuffer wrapper fixes from later in the series
    - Use correct physical slice offset for UMS/CMS surfaces on Gen7

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-03-02 11:35:24 +13:00
Chris Forbes
575d3870bb mesa: implement TexImage*Multisample
V2: - fix formatting issues
    - generate GL_OUT_OF_MEMORY if teximage cannot be allocated
    - fix for state moving from texobj to image

V3: - remove ridiculous stencil hack
    - alter format check to not allow a base format of STENCIL_INDEX
    - allow width/height/depth to be zero, to deallocate the texture
    - dont forget to call _mesa_update_fbo_texture

V4: - fix indentation
    - don't throw errors on proxy texture targets

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2013-03-02 11:35:24 +13:00
Chris Forbes
61d42ffef4 mesa: support multisample textures in framebuffer completeness check
- sample count must be the same on all attachments
- fixedsamplepositions must be the same on all attachments
(renderbuffers have fixedsamplepositions=true implicitly; only
multisample textures can choose to have it false)

V2: - fix wrapping to 80 columns, debug message, fix for state moving
      from texobj to image.
    - stencil texturing tweaks tidied up and folded in here.

V3: - Removed silly stencil hacks entirely; the extension doesn't
      actually make stencil-only textures legal at all.
    - Moved sample count / fixed sample locations checks into
      existing attachment-type-specific blocks, as suggested by Eric

V4: - Removed stencil hacks which were missed in V3 (thanks Eric)
    - Don't move the declaration of texImg; only required pre-V3.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
[V2] Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-03-02 11:35:22 +13:00
Chris Forbes
032896cbf9 i965: expose sample positions
Moves the definition of the sample positions out of
gen6_emit_3dstate_multisample, and unpacks them in
gen6_get_sample_position.

V2: Be consistent about `sample position` rather than `location`.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2013-03-02 11:35:20 +13:00
Chris Forbes
569c4a9f1c i965: add support for sample mask on Gen6+
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-03-02 11:35:17 +13:00
Chris Forbes
1822496f3a mesa: implement sample mask
V2: - fix multiline comment style
    - stop using ASSERT_OUTSIDE_BEGIN_END_AND_FLUSH since that
      doesn't exist anymore.

V3: - check for the extension being enabled
    - tidier flagging of _NEW_MULTISAMPLE
    - fix weird indentation in get.c

V4: - move flush later in SampleMaski()

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-03-02 11:35:16 +13:00
Chris Forbes
7c1017e292 mesa: implement GetMultisamplefv
Actual sample locations deferred to a driverfunc since only the driver
really knows where they will be.

V2: - pass the draw buffer to the driverfunc; don't fallback to pixel
      center if driverfunc is missing.
    - rename GetSampleLocation to GetSamplePosition
    - invert y sample position for winsys FBOs, at Paul's suggestion

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-03-02 11:35:13 +13:00
Chris Forbes
abb5429537 i965: expose new max sample counts
V2: For now, only expose a depth sample count of 1, since there are
possible unresolved interactions with HiZ.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-03-02 11:35:08 +13:00
Chris Forbes
db5d5c30a6 mesa: add new max sample count state
- GL_MAX_COLOR_TEXTURE_SAMPLES
- GL_MAX_DEPTH_TEXTURE_SAMPLES
- GL_MAX_INTEGER_SAMPLES

V2: initialize limits to 1 in _mesa_init_constants as suggested by Brian
and Paul

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-03-02 11:34:58 +13:00
Chris Forbes
ffb53b4f03 glsl: add support for ARB_texture_multisample
V2: - emit `sample` parameter properly for multisample texelFetch()
    - fix spurious whitespace change
    - introduce a new opcode ir_txf_ms rather than overloading the
      existing ir_txf further. This makes doing the right thing in
      the driver somewhat simpler.

V3: - fix weird whitespace

V4: - don't forget to include the new opcode in tex_opcode_strs[]
      (thanks Kenneth for spotting this)

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
[V2] Reviewed-by: Eric Anholt <eric@anholt.net>
[V2] Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-03-02 11:33:54 +13:00
Chris Forbes
16af0aca09 tests: add ARB_texture_multisample enums to table
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-03-02 11:33:42 +13:00
Chris Forbes
d04a4dd003 mesa: add texobj support for ARB_texture_multisample
Adds the new texture targets, and per-image state for GL_TEXTURE_SAMPLES
and GL_TEXTURE_FIXED_SAMPLE_LOCATIONS.

V2: - Allow multisample texture targets in glInvalidateTexSubImage too.
      This was already partly there, but I missed it the first time around
      since the interaction is defined in a newer extension. Fixed weird
      indentation.
    - Allow multisample array textures in glFramebufferTextureLayer.
      This was overlooked as the tests originally only used 2d
      multisample textures.

V3: - Set min/mag filters sensibly for multisample textures. This
      can't actually be changed by the user, so it's more sensible to
      initialize it correctly than to hack around it being bogus later.

V4: - Tidy up initial min/mag filter setup. Setup in
      _mesa_initialize_texture_object was bogus, but benign since
      finish_texture_init() clobbered everything with correct values. For V4,
      just do the setup in finish_texture_init().

V5: - Don't break glPopAttrib(GL_TEXTURE_BIT)

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
[V2] Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-03-02 11:33:27 +13:00
Chris Forbes
0f83e415e4 glapi: add ARB_texture_multisample
Adds new enums, dispatch machinery, and stubs for the 4 new entrypoints.

V2: - Drop placeholder
    - Align enum values
    - Remove explicit exec=mesa; it *is* the dispatch flavor we want,
      but it's also the default. I misunderstood how this worked before;
      after actually reading the generator it makes good sense.

V3: - Squash in stubs for new entrypoints, and dispatch_sanity tweaks,
      so we don't get build breakage between those patches.

V4: - Fix various remaining whitespace issues

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
[1/3 V2] Reviewed-by: Matt Turner <mattst88@gmail.com>
[V3] Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-03-02 11:33:20 +13:00
Eric Anholt
c0674fa5cd intel: Use the new "ctx" local variable I just added some more.
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
2013-03-01 12:10:22 -08:00
Eric Anholt
e15c21a957 i965: Make sRGB-capable framebuffers by default.
The GLX extension lets you expose visuals that explicitly guarantee you
that the GL_FRAMEBUFFER_SRGB_CAPABLE flag will be set, but we can set
the flag even while the visual doesn't provide the guarantee.  This
appears to be consistent with other implementations, as we've seen
several apps now that don't require an srgb visual and assume sRGB will
work without checking the GL_FRAMEBUFFER_SRGB_CAPABLE flag.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55783
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60633
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick@intel.com>
2013-03-01 12:10:16 -08:00
Eric Anholt
973ddc897d intel: Fix software copying of miptree faces for weird formats.
Now that we have W-tiled S8, we can't just region_map and poke at bits --
there has to be some swizzling.  Rely on intel_miptree_map to get that job
done.  This should also get the highest performance path we know of for the
mapping (interesting if I get around to finishing movntdqa some day).

v2: Fix stale name of the bit in a comment.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2013-03-01 11:50:03 -08:00
Eric Anholt
6d6bd2ac7c intel: Add a flag for miptree mapping to disable transcoding.
I want to reuse intel_miptree_map() to replace some region mapping that's
broken for separate stencil, but doing so would result in new demands on
ETC transcode that we actually don't want to happen.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2013-03-01 11:50:03 -08:00
Eric Anholt
e63c959451 i965: Add WARN_ONCE for depthstencil workarounds we shouldn't be hitting.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2013-03-01 11:50:03 -08:00
Alex Deucher
a40ba43d78 r600g: enable CP DMA on 6xx
Tested across several 6xx parts, no piglit regressions.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-03-01 12:11:31 -05:00
Marek Olšák
58bd926d9e r600g: don't require dword alignment with CP DMA for buffer transfers
which is a leftover from the days when we used streamout to copy buffers

Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>
2013-03-01 13:46:32 +01:00
Marek Olšák
89e2898e9e r600g: always map uninitialized buffer range as unsynchronized
Any driver can implement this simple and efficient optimization.
Team Fortress 2 hits it always. The DISCARD_RANGE codepath is not even used
with TF2 anymore, so we avoid a ton of useless buffer copies.

Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>

NOTE: This is a candidate for the 9.1 branch.
2013-03-01 13:46:32 +01:00
Marek Olšák
44f37261fc gallium/util: add helper code for 1D integer range
Reviewed-by: Brian Paul <brianp@vmware.com>

v2: cosmetic changes based on Brian's review

Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>

NOTE: This is a candidate for the 9.1 branch. (the next patch depends on it)
2013-03-01 13:46:32 +01:00
Marek Olšák
8f192a3c9e r600g: cleanup deprecated register tables
These registers are either already emitted elsewhere or moved to start_cs.

Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>
2013-03-01 13:46:32 +01:00
Marek Olšák
f0636bc982 r600g: unify vgt states
The states were split because we thought it caused a hardlock. Now we know
the hardlock was caused by something else and has since been fixed.

Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>
2013-03-01 13:46:32 +01:00
Marek Olšák
e5a250fdf9 r600g: flush and invalidate htile cache when appropriate
Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>

NOTE: This is a candidate for the 9.1 branch.
2013-03-01 13:46:32 +01:00
Marek Olšák
6f25de6711 r600g: atomize streamout enabling
This doesn't fix any issue we know of, but there indeed is a week spot
in draw_vbo where streamout can fail. After streamout is enabled,
the need_cs_space call can flush the context, which causes the streamout
to be disabled right after it was enabled and bad things happen.

One way to fix it is to atomize the beginning part, so that no context flush
can happen between streamout enabling and the first drawing.

Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>
2013-03-01 13:46:32 +01:00
Marek Olšák
9dd18f43a4 r600g: use async DMA with a non-zero src offset
probably a typo

Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>

NOTE: This is a candidate for the 9.1 branch.
2013-03-01 13:46:32 +01:00
Marek Olšák
c77917d35f r600g: pad the DMA CS to a multiple of 8 dwords
Tested-by: Andreas Boll <andreas.boll.dev@gmail.com>

NOTE: This is a candidate for the 9.1 branch.
2013-03-01 13:46:32 +01:00
Jordan Justen
782d4f0f3c intel: Enable __DRI_API_OPENGL_CORE api with dri2 contexts
Without this set, dri_util.c:dri2CreateContextAttribs
will reject requests to create a context with
__DRI_API_OPENGL_CORE.

This prevents a 3.2 core profile context from being created
even when MESA_GL_OVERRIDE_VERSION=3.2 is used.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-28 21:51:00 -08:00
Jordan Justen
fde59a27fb intel: update max versions based on MESA_GL_VERSION_OVERRIDE
If the override is version is >= 3.1, then update the
max_gl_core_version. Otherwise, update max_gl_compat_version.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-28 21:50:56 -08:00
Jordan Justen
c4e059a359 mesa version: add _mesa_get_gl_version_override
This will allow other code to get access to the override
version before a context is available.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-28 21:50:50 -08:00
Jordan Justen
500b69e797 glsl: allow GLSL compiler version to be overridden to 1.50
Although GLSL 1.50 compiler support is not available,
this change will allow MESA_GLSL_VERSION_OVERRIDE=150 to be
used while 1.50 support is being developed.

Since no drivers claim 1.50 GLSL support, this change should
only impact Mesa when MESA_GLSL_VERSION_OVERRIDE=150 is set.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-28 21:49:59 -08:00
Matt Turner
4154ac066f i965/fs: Put immediate operand as src2
Immediate operands can only be src2 in 2-source instructions. Fixes
piglit failures since 0a1d145e (oops!).

Spotted-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-02-28 16:29:30 -08:00
Chad Versace
809fdc211f intel: Remove intel_mipmap_tree::wraps_etc
The field was equivalent to (etc_format != MESA_FORMAT_NONE), and
therefore duplicate information.

This patch removes field and replaces all references to it with
`etc_format != MESA_FORMAT_NONE`.

No Piglit ETC test regresses on Intel Sandybridge.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-02-28 15:22:41 -08:00
Matt Turner
c001985cbf ir_to_mesa: Translate ir_triop_lrp to OPCODE_LRP.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-28 13:19:00 -08:00
Matt Turner
428503fcdf i965/vs: Assert that ir_triop_lrp was lowered.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-28 13:19:00 -08:00
Matt Turner
f78a7ff6b2 i965/fp: Use the LRP instruction for OPCODE_LRP.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-28 13:19:00 -08:00
Kenneth Graunke
0a1d145e5f i965/fs: Use the LRP instruction for ir_triop_lrp when possible.
v2 [mattst88]:
   - Add BRW_OPCODE_LRP to list of CSE-able expressions.
   - Fix op_var[] array size.
   - Rename arguments to emit_lrp to (x, y, a) to clear confusion.
   - Add LRP function to brw_fs.cpp/.h.
   - Corrected comment about LRP instruction arguments in emit_lrp.
v3 [mattst88]:
   - Duplicate MAD code for LRP instead of using a function pointer.
   - Check for != GRF instead of == IMM in emit_lrp.
   - Lower LRP on gen < 6.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

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2013-02-28 13:19:00 -08:00