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Author SHA1 Message Date
Erik Faye-Lund
1fbec9f532 util/format: document NONE swizzle 
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26192>
 2023-12-01 07:53:58 +00:00
ratatouillegamer
5f7aa0e012 hasvk: Enable hasvk override Vulkan API Version for Brawlhalla 
Brawlhalla runs good with DXVK 2.0+, it can be enable as default
avoiding to use OpenGL Brawlhalla renderer.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26433>
 2023-12-01 07:18:10 +00:00
ratatouillegamer
9de6928746 hasvk: Add Vulkan API version override 
This allows to use a driconf to override the API version and expose Vulkan 1.3.
That can be used in conjunction with certain games like for example Brawlhalla
which benefits from some DXVK +2.0 features.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26433>
 2023-12-01 07:18:10 +00:00
Gert Wollny
c13de0509c r600/sfn: Don't try to re-use iterators when the set is made empty 
It seems with libc++ the iterators are invalidated when the set
is emptied during iterating over it.

Fixes: 05fab97 (r600/sfn: Don't try to re-use the iterator when uses is updated)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7931

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26420>
 2023-12-01 06:37:30 +00:00
Qiang Yu
b16017d080 nir: fix load layer id system_values_read info gather 
Otherwise radeons+ACO compilation fail.

Fixes: 32ee6376ad ("nir: add lowering from FS LAYER input to LAYER_ID sysval")
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26422>
 2023-12-01 03:17:57 +00:00
Rohan Garg
a499be0ee3 intel/genxml: Update IDD for new fields 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Rohan Garg
c916038b89 intel/genxml: Update COMPUTE_WALKER_BODY for xe2 
Reworks:
 * Caio: Change patch to only add COMPUTE_WALKER_BODY and
   EXECUTE_INDIRECT_DISPATCH (that uses it).

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Rohan Garg
cc2dce82bc intel: Set a preferred SLM size for LNL 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Jordan Justen
16483cd4bc iris: xe2 doesn't have INTERFACE_DESCRIPTOR_DATA::BarrierEnable 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Rohan Garg
ef1c1ca821 intel/genxml: Add the preferred slm size enum for xe2 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Jordan Justen
1e9972991c anv, iris: Update INTERFACE_DESCRIPTOR_DATA programming for xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Jordan Justen
bdb9c70f84 intel/genxml: Update INTERFACE_DESCRIPTOR_DATA for xe2 
Reworks:
 * Caio: Remove "Mask Stack Exception Enable", not present in BSpec.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Jordan Justen
d95bbf35c9 anv: Set COMPUTE_WALKER Message SIMD field 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Jordan Justen
59dc9b1df6 iris: Set COMPUTE_WALKER Message SIMD field 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Jordan Justen
aafdf59dfe intel/genxml: Update COMPUTE_WALKER for xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Jordan Justen
064bdecb36 intel/compiler: Define XE2 compiler enum 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390>
 2023-12-01 02:36:12 +00:00
Tatsuyuki Ishi
eb0419a1aa radv: Remove aspect mask "expansion" for copy_image. 
The Vulkan spec says multi-planar images can only be copied on a
per-plane basis. The COLOR_BIT to "all planes" expansion applies to
image memory barriers which is completely unrelated.

Remove the expansion logic to simplify the code. Add assertions to
clearly describe the invariant.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26364>
 2023-12-01 01:52:04 +00:00
Marek Olšák
7ffb65f935 ac: add an IB parser that gathers context rolls 
This is an important performance bottleneck analysis tool.

Try it with radeonsi: AMD_ROLLS=filename app

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
 2023-12-01 01:15:55 +00:00
Marek Olšák
f0cb8852a4 ac: move the IB parsers into ac_parse_ib.c 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
 2023-12-01 01:15:55 +00:00
Marek Olšák
c5fe2780e6 ac: rename ac_parse_ib.c -> ac_ib_parser.c 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
 2023-12-01 01:15:55 +00:00
Peyton Lee
95c933c8b7 winsys, amdgpu, drm: add VPE submission handle 
Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
 2023-12-01 00:23:38 +00:00
Peyton Lee
a212e9bdbf amd, radeonsi: supports post processing entrypoint 
create a new decoder for handling post processing

Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
 2023-12-01 00:23:38 +00:00
Peyton Lee
ed176e2c71 amd, radeonsi: add si_vpe.c with helper functions of VPE lib 
Signed-off-by: Peyton Lee <peytolee@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
 2023-12-01 00:23:38 +00:00
Peyton Lee
3ec397819e amd: add new hardware ip for vpe 
Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
 2023-12-01 00:23:38 +00:00
Peyton Lee
17c20ceda7 amd,radeonsi: add libvpe 
Signed-off-by: Peyton Lee <peytolee@amd.com>
Signed-off-by: Alan Liu <haoping.liu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
 2023-12-01 00:23:38 +00:00
Peyton Lee
6b441ef6ab frontends, va: add new parameters of post processor 
Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713>
 2023-12-01 00:23:38 +00:00
Jesse Natalie
be05c9458a microsoft/clc: Fix image lowering pass to only erase variables at the end 
Otherwise, if a variable has multiple derefs in a shader, we'll crash
trying to remove it a second time. No idea how that can happen though,
seems derefs got sunk by opt_dead_cf.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26435>
 2023-11-30 23:32:08 +00:00
Lynne
aff59c63eb radv: change queue family order in radv_get_physical_device_queue_family_properties 
Fixes: 748b7f80ef ("radv: Move sparse binding into a dedicated queue.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26428>
 2023-11-30 22:45:49 +00:00
José Roberto de Souza
42dd48e933 anv: Fix vm bind of DRM_XE_VM_BIND_FLAG_NULL 
In this case bo is NULL so application was crashing when it was trying
to get the alloc_flags of bo to get the intel_device_info_pat_entry.

Fixes: 1a0d3504d5 ("anv: Fill PAT fields in Xe KMD gem_create and vm_bind uAPIs")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26430>
 2023-11-30 22:22:41 +00:00
Rhys Perry
5bc27e80c9 ac/nir: fix 32-bit offset global access optimization 
Since 38cff03e58 ("radv: use nir_lower_conv64"), u2u64(a) is replaced
with pack_64_2x32_split(a, 0).

fossil-db (navi31):
Totals from 1203 (1.52% of 79330) affected shaders:
MaxWaves: 33685 -> 33813 (+0.38%)
Instrs: 1407031 -> 1374689 (-2.30%); split: -2.32%, +0.02%
CodeSize: 7088652 -> 6917320 (-2.42%); split: -2.43%, +0.01%
VGPRs: 69276 -> 68988 (-0.42%); split: -0.43%, +0.02%
SpillSGPRs: 982 -> 977 (-0.51%); split: -0.92%, +0.41%
Latency: 12536511 -> 12451605 (-0.68%); split: -0.94%, +0.27%
InvThroughput: 2456803 -> 2431241 (-1.04%); split: -1.09%, +0.05%
VClause: 27624 -> 27832 (+0.75%); split: -1.88%, +2.64%
SClause: 31757 -> 32702 (+2.98%); split: -0.53%, +3.51%
Copies: 90923 -> 91238 (+0.35%); split: -1.47%, +1.81%
Branches: 25127 -> 25128 (+0.00%); split: -0.00%, +0.01%
PreSGPRs: 46025 -> 46068 (+0.09%); split: -0.53%, +0.62%
PreVGPRs: 53944 -> 53488 (-0.85%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26402>
 2023-11-30 21:50:21 +00:00
Rhys Perry
10ba06960f ac/nir: ignore 8/16-bit global access offset 
This was found by inspection, I'm not sure it can even happen.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26402>
 2023-11-30 21:50:21 +00:00
Caio Oliveira
bbb12dbbf9 intel/compiler: Add a few tests to opt_predicated_break 
v2 (idr): Fix expectations BottomBreakWithContinue. opt_predicated_break
will remove the IF and make the CONTINUE predicated.

v3 (idr): Temporarily disable the one test that fails.

v4 (idr): Free strings allocated by open_memstream. Fixes gitlab CI
failures in debian-testing-asan.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Caio Oliveira
0b072c5351 intel/compiler: Sort lists of succs and preds in CFG dump output 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Caio Oliveira
47c5656f0e intel/compiler: Allow dumping CFG to a specific FILE* 
Add optional argument for both cfg and block dump() function to pass
a FILE*.  Default behavior remains dumping to stderr.

v2 (idr): Don't add the new test framework in this commit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Caio Oliveira
21cf9323f0 intel/compiler: Add a few more helpers to fs_builder 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Ian Romanick
c0ecc0d70b intel/compiler: Don't promote CFG link types when removing a block 
Imagine 3 blocks A, B, and C. A has a physical link to B, and B has a
logical link to C. Previous to this commit, if B were removed, A would
get a logical link to C. This is not correct.

This was specifically observed to occur when block A was a DO block and
B was the WHILE block. The DO block would have two logical successors,
and that is completely invalid.

v2: Assert that the links from A-to-B and B-back-to-A are the same
kind. Suggested by Caio.

v3: Assume the successor and predecessor lists are well formed. Use this
to simplify the logic. Suggested by Caio. Add checks to cfg_t::validate
to ensure the lists are well formed.

v4: Remove (now unused) bblock_link_invalid. Suggested by Curro.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Ian Romanick
77c0c1ce54 intel/compiler: Don't create extra CFG links when deleting a block 
The previous is_successor_of and is_predecessor_of checks prevented
creating a physical link when a logical link already existed. However, a
logical link could be added when a physical link already existed. This
change causes an existing physical link to be "promoted" to a logical
link.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Ian Romanick
7e842a75ac intel/compiler: Don't create extra CFG links in opt_predicated_break 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Ian Romanick
bbd7729993 intel/compiler: Delete bidirectional block links in opt_predicated_break 
Previously when earlier_block->children.make_empty() was called, the
child blocks would still have links back to earlier_block.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Ian Romanick
5842829380 intel/compiler: Limit scope of cur_endif variable 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Ian Romanick
02f9bbf6f3 intel/compiler: Add basic CFG validation 
v2: Use _mesa_shader_stage_to_abbrev(stage) instead of
stage_abbrev. Noticed by Caio and GCC. That's what I get for not
recompiling after rebasing. Wrap cfg_t::validate in NDEBUG
magic. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Ian Romanick
19db6f1cd9 intel/vec4: Don't emit an empty ELSE 
This matches the behavior of fs_visitor::nir_emit_if.

This is not technically wrong, but the cfg_t generates some invalid
parent / child links in this case.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25216>
 2023-11-30 20:58:05 +00:00
Rohan Garg
f3d99e3535 anv: introduce ANV_TIMESTAMP_REWRITE_INDIRECT_DISPATCH 
In order to rewrite timestamps for indirect dispatch's, instroduce a
ANV_TIMESTAMP_REWRITE_INDIRECT_DISPATCH that repacks the PostSync field
for a EXECUTE_INDIRECT_DISPATCH.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg
9dd49e7a63 anv: memcpy the thread dimentions only when they're on the CPU 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg
d161e3c2e2 iris: Emit a EXECUTE_INDIRECT_DISPATCH when available 
On newer platforms (Arrowlake and above) we can issue a
EXECUTE_INDIRECT_DISPATCH that allows us to:

  * Skip issuing mi load/store instructions for indirect parameters

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg
580728564e anv: Emit a EXECUTE_INDIRECT_DISPATCH when available 
On newer platforms (Arrowlake and above) we can issue a
EXECUTE_INDIRECT_DISPATCH that allows us to:
  * Skip issuing mi load/store instructions for indirect parameters

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg
6d4f43f0d6 anv: Emit EXECUTE_INDIRECT_DRAW when available 
On newer platforms (Arrowlake and above) we can issue a
EXECUTE_INDIRECT_DRAW that allows us to:
  * Skip issuing mi load/store instructions for indirect parameters
  * Skip doing the indirect draw unroll on the CPU side when the
    appropriate stride is passed

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg
7a9e82e82f genxml/12.5: Add the EXECUTE_INDIRECT_DISPATCH instruction 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:45 +00:00
Rohan Garg
4229757309 genxml/12.5: Add the EXECUTE_INDIRECT_DRAW instruction 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:44 +00:00
Rohan Garg
6e060d99ba intel/dev: Add a bit for when the HW can do a indirect draw/dispatch unroll 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421>
 2023-11-30 17:01:44 +00:00