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Author SHA1 Message Date
Rhys Perry
a1022dbf07 aco: use some helpers in GFX10 hazard workarounds 
No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18270>
 2022-09-30 11:44:38 +00:00
Rhys Perry
a4f6acece1 aco: improve VMEMtoScalarWriteHazard s_waitcnt mitigation 
fossil-db (navi10):
Totals from 171 (0.13% of 134563) affected shaders:
Instrs: 69348 -> 69144 (-0.29%)
CodeSize: 381112 -> 380296 (-0.21%)
Latency: 451534 -> 451387 (-0.03%)
InvThroughput: 88692 -> 88686 (-0.01%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18270>
 2022-09-30 11:44:38 +00:00
Rhys Perry
2bd16256a6 aco: fix VMEMtoScalarWriteHazard s_waitcnt mitigation 
It doesn't make sense for a "s_waitcnt vmcnt(0)" to affect a store or DS
instruction.

LLVM checks for "s_waitcnt vmcnt(0) lgkmcnt(0) expcnt(0)" but ignores
s_waitcnt_vscnt (which I assume is a bug).

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: bcf94bb933 ("aco: properly recognize that s_waitcnt mitigates VMEMtoScalarWriteHazard")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18270>
 2022-09-30 11:44:38 +00:00
Georg Lehmann
bfb12a3b6a nir/opt_algebraic: Optimize more (a cmp b ? a : b) to min/max. 
Foz-DB Navi21:
Totals from 112 (0.08% of 134913) affected shaders:
CodeSize: 1618384 -> 1618172 (-0.01%); split: -0.06%, +0.04%
Instrs: 307695 -> 307535 (-0.05%); split: -0.05%, +0.00%
Latency: 3590228 -> 3589658 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 563692 -> 563447 (-0.04%); split: -0.05%, +0.01%
Copies: 24541 -> 24519 (-0.09%); split: -0.10%, +0.01%
Branches: 13480 -> 13468 (-0.09%)

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18548>
 2022-09-30 11:10:52 +00:00
Rajnesh Kanwal
d0d90b4de9 pvr: Implement vkGetEventStatus API. 
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18864>
 2022-09-30 11:01:47 +00:00
Rajnesh Kanwal
a125accd16 pvr: Add assert to check for non-NULL binding_desc. 
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18866>
 2022-09-30 10:52:51 +00:00
Rajnesh Kanwal
a12395c464 pvr: Call VALGRIND_FREELIKE_BLOCK before unmapping to avoid use after free. 
Fixes: CID 1503261.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18866>
 2022-09-30 10:52:51 +00:00
Rajnesh Kanwal
cc530255bb pvr: Fix Unintentional integer overflow (OVERFLOW_BEFORE_WIDEN) errors. 
Fixes: CID 1503255, 1503258, 1503265, 1503268, 1504078, 1507509.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18866>
 2022-09-30 10:52:51 +00:00
Rajnesh Kanwal
1021550e20 pvr: Zero init pbe_cs_words to avoid passing on garbage. 
In case if the surface->resolve_type is not PVR_RESOLVE_TYPE_PBE
then we do not setup pbe_cs_words in which case we might end up
using garbage values.

Fixes: CID 1515466.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18866>
 2022-09-30 10:52:51 +00:00
Rajnesh Kanwal
3fbecd485e pvr: Remove dead code from pvr_perform_start_of_render_clears. 
Logically the hw_render would never be NULL so the if block is
never used and can be removed.

Fixes: CID1503270.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18866>
 2022-09-30 10:52:51 +00:00
Rajnesh Kanwal
d1eb75ecec pvr: Remove framebuffer NULL check from pvr_CmdBeginRenderPass2. 
Framebuffer can not be NULL in pvr_CmdBeginRenderPass2.

Fixes: CID 1503259.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18866>
 2022-09-30 10:52:51 +00:00
Rajnesh Kanwal
6cef99c536 pvr: Remove redundant assignment error.instruction. 
Fixes: CID 1503256.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18866>
 2022-09-30 10:52:51 +00:00
Rajnesh Kanwal
4f965ad8ee pvr: Remove redundant instruction buffer check. 
Fixes: CID 1503273.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18866>
 2022-09-30 10:52:51 +00:00
Rajnesh Kanwal
568b7b4635 pvr: Convert attachment indexes to unsigned. 
This commit converts attachment indexes used in renderpass to unsigned
and uses VK_ATTACHMENT_UNUSED for unused attachments instead of -1.

Also fixes some signed to unsigned comparisons.

Fixed: CID 1515587, 1515590, 1515597, 1515604.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18866>
 2022-09-30 10:52:51 +00:00
Tapani Pälli
60be71aeaa anv: limit to default fast clear color when image used for transfer 
v2: use vk_image_layout_to_usage_flags for detecting
    transfer usage (Nanley)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7189
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18836>
 2022-09-30 10:14:01 +00:00
Rajnesh Kanwal
35c40c64c8 pvr: Handle indirect buffer address in pvr_setup_descriptor_mappings. 
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18872>
 2022-09-30 10:55:27 +01:00
Rajnesh Kanwal
faf1ac8307 pvr: implement vkcmddispatchindirect api. 
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18872>
 2022-09-30 10:55:27 +01:00
Samuel Pitoiset
f5c50f496c radv: enable the unified heap on APUs for Red Dead Redemption 2 
This seems to resolve the memory explosion without hurting performance.
This workaround is only applied for native Vulkan.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18884>
 2022-09-30 11:01:50 +02:00
Samuel Pitoiset
0974b67a6e radv: add a new drirc option to enable a unified heap on APUs 
This option (radv_enable_unified_heap_on_apu) allows to force the
driver to expose only one heap of VRAM because some games seem to
perform better with that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18884>
 2022-09-30 11:01:48 +02:00
Mike Blumenkrantz
31d38d1882 zink: enable glthread by default 
huge perf gains.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18858>
 2022-09-30 02:16:02 +00:00
Mike Blumenkrantz
8da9e65500 pipe-loader: fix zink driinfo header path 
this feels like a compiler bug, but somehow just specifying the
shorter path ends up with a broken/partial header include

Fixes: d760a9151b ("gallium: Learn about kopper")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18858>
 2022-09-30 02:16:02 +00:00
Mike Blumenkrantz
966d6b738e zink: export PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18858>
 2022-09-30 02:16:02 +00:00
Mike Blumenkrantz
12569a390f zink: export PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18858>
 2022-09-30 02:16:02 +00:00
Mike Blumenkrantz
af775f842c zink: fix/improve handling for multi-component bitfield ops 
the original improvement for this correctly handled cases where
the offset/count values were swizzled with .xxxx, but it was broken
for any other swizzling

this adds a nir pass to more easily manipulate the swizzles and rewrite
the multi-component ops as multiple ops with the swizzled params

fixes #6697

Fixes: 8e97f51c67 ("zink: handle swizzled offset/count values for shader bitfield ops")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18706>
 2022-09-30 01:52:47 +00:00
Dave Airlie
111bf8bfee llvmpipe/fs: convert outputs handling to explicit api 
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18876>
 2022-09-30 01:22:42 +00:00
Dave Airlie
5b83357ac5 llvmpipe/fs: cleanup some remaining mask handling and reuse types 
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18876>
 2022-09-30 01:22:42 +00:00
Dave Airlie
b9a0ec0c67 llvmpipe/fs: handle explicit types around blending and c/zs bufs calcs 
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18876>
 2022-09-30 01:22:42 +00:00
Dave Airlie
3137f4fad1 llvmpipe/fs: use explicit api in viewport code. 
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18876>
 2022-09-30 01:22:42 +00:00
Dave Airlie
38907a40ab llvmpipe/fs: pass mask type to alpha to coverage handler 
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18876>
 2022-09-30 01:22:42 +00:00
Dave Airlie
e28db68e53 llvmpipe/fs: add sample position type to the interp interface 
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18876>
 2022-09-30 01:22:42 +00:00
Dave Airlie
ff02d042aa llvmpipe/fs: port depth code to opaque pointer api 
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18876>
 2022-09-30 01:22:42 +00:00
Dave Airlie
694104b776 llvmpipe/fs: pass explicit mask_type into interp code. 
This is so it is known for explicit pointer support

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18876>
 2022-09-30 01:22:42 +00:00
Dave Airlie
637652a97f llvmpipe/fs: add mask_type for mask_store accesses. 
This adds and passes around the type for mask stores.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18876>
 2022-09-30 01:22:42 +00:00
Dave Airlie
b36160689f gallivm/struct: add opaque ptr friendly pointer accessors. 
These just add explicit types.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18876>
 2022-09-30 01:22:42 +00:00
Kenneth Graunke
b61b1d5a4c Revert "intel/compiler: Vectorize gl_TessLevelInner/Outer[] writes" 
This reverts commit abba55382f.
The assertions I added late in the process broke shader-db, and my
quick fix broke CI, so let's just revert it for now and I'll resubmit
this later when it's working better.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7385
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18895>
 2022-09-29 17:39:18 -07:00
Eric Anholt
1a286837bc freedreno/ir3: Validate our scheduling DAGs after construction. 
This gives us some better explanation of a stack overflow in ir3_postsched
with shader-db:

IR3_SHADER_DEBUG=nouboopt ./run shaders/nexuiz/46.shader_test

DAG validation failed at:
  0x55f6570e8460: 0079:0107:002: 	_meta:collect r1.w (wrmask=0xff), r1.w, r2.x, r2.y, r2.z, r2.w, r3.x, r3.y, r3.z, false-deps:_[0098:0126:000:  mov.u32u32], _[0112:0143:000:  mov.u32u32], _[0087:0113:000:  mov.u32u32], _[0113:0144:000:  mov.u32u32], _[0099:0127:000:  mov.u32u32], _[0088:0114:000:  mov.u32u32]

Nodes in stack:
  0x55f657102050: 0079:0103:009: 	mov.u32u32 r1.w, r0.x, right=_[0080:0104:009:  mov.u32u32]

  0x55f6570e8460: 0079:0107:002: 	_meta:collect r1.w (wrmask=0xff), r1.w, r2.x, r2.y, r2.z, r2.w, r3.x, r3.y, r3.z, false-deps:_[0098:0126:000:  mov.u32u32], _[0112:0143:000:  mov.u32u32], _[0087:0113:000:  mov.u32u32], _[0113:0144:000:  mov.u32u32], _[0099:0127:000:  mov.u32u32], _[0088:0114:000:  mov.u32u32]

  0x55f657075f80: 0083:0108:007: 	samgq (f32)(xyz)r0.z (wrmask=0x7), r1.w (wrmask=0xff), s#3, t#3

  0x55f657051b60: 0104:0134:008: 	ldc.offset0 r3.x (wrmask=0xf), imm[0.000000,0,0x0], r9.w

  0x55f657103040: 0112:0143:000: 	mov.u32u32 r9.w, r0.x, right=_[0113:0144:000:  mov.u32u32]

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6656>
 2022-09-29 23:40:18 +00:00
Eric Anholt
5d0050c8bf util/dag: Add a validation function. 
I experienced a circular dag in freedreno, and wanted a way to see what
was going wrong.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6656>
 2022-09-29 23:40:18 +00:00
Eric Anholt
984aa0ac9a util/dag: Move the callback function pointer to the state. 
No sense passing it as a recursive argument when we have this storage
right there.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6656>
 2022-09-29 23:40:18 +00:00
Mike Blumenkrantz
004c5b60ca glthread: handle DeleteBuffers(n=-1) gracefully 
this is a valid error condition

cc: mesa-stable

fixes:
GTF-GL46.gtf21.GL2FixedTests.buffer_objects.buffer_objects

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18856>
 2022-09-29 22:05:06 +00:00
Mike Blumenkrantz
171b2a16b5 glthread: use signed vertex buffer offsets when available, don't require them 
this is a great memory-saving optimization for drivers that support it,
but for drivesr that can't, it ends up taking slower paths instead
of just consuming more memory

but the year is 2022. we have all the memory. so use more memory if signed
offsets aren't supported

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18856>
 2022-09-29 22:05:06 +00:00
Sil Vilerino
248e3ceba2 d3d12: Style variable fix in d3d12_video_decoder_prepare_dxva_slices_control_av1 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18875>
 2022-09-29 15:50:04 -04:00
Sil Vilerino
aa1afc3766 d3d12: Fix aliased usage of m_SliceControlBuffer in d3d12_video_decoder_prepare_dxva_slices_control_XXXX 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18875>
 2022-09-29 15:50:04 -04:00
Sil Vilerino
1222503ef3 d3d12: Support more video formats 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>

Adds support for P010 Encoding and Decoding
Also adds support for RGBA/RGBX UNORM/UINT in the video processor

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18875>
 2022-09-29 15:50:04 -04:00
Sil Vilerino
af8f730d8d d3d12: Add support for AV1 Video Decode 
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18875>
 2022-09-29 15:50:04 -04:00
Sil Vilerino
f2fc9996d3 frontends/va: Fix AV1 decode qm_* parameters reading from VADecPictureParameterBufferAV1 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>

Those are being read with | 0xF, but instead should be & 0xF to clear the bits above 4 (the field is 4 bits in size)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18875>
 2022-09-29 15:50:04 -04:00
Sil Vilerino
4bab5b0b50 frontends/va: Use is_video_format_supported in vlVaVidEngineBlit instead of format list 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18875>
 2022-09-29 15:50:04 -04:00
Sil Vilerino
e91636ae26 frontends/va: Support AV1 Decode with multiple tiles (num_elements > 1) in a single VASliceParameterBufferAV1 buffer 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18875>
 2022-09-29 15:50:04 -04:00
Sil Vilerino
d5b4dec033 frontends/va: Add more params from VADecPictureParameterBufferAV1 and VASliceParameterBufferAV1 to pipe_av1_picture_desc 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18875>
 2022-09-29 15:50:04 -04:00
Marcin Ślusarz
9bac88856d intel/compiler: fix loading of draw_id from task & mesh payload 
Previously both destination and source were floats, so no casting was
performed, but with 7664c85b1d source register was reinterpreted as
unsigned integer, so MOV started casting that integer to float.

Fixes: 7664c85b1d ("intel/compiler: Create and use struct for TASK and MESH thread payloads")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18886>
 2022-09-29 17:17:25 +00:00
Dmitry Osipenko
e5631add0d ci/virgl: Enable virgl-iris-traces 
All virgl-iris-traces tests are passing now after the crosvm revup that
fixed crosvm crash and after updating test checksums. Enable auto-testing
for the virgl-iris-traces pipeline stage.

Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18693>
 2022-09-29 16:45:04 +00:00