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Author SHA1 Message Date
Kenneth Graunke
e40fafa991 iris: Defer stream output target space allocation until set time 
In the future, Marek is planning to make u_threaded_context call
create_stream_output_target() from a different thread than the main
driver thread, which means that we can't safely use uploaders there.

To prepare for this eventual future, just defer the allocation of
the offset BO 'til later.  It's a very small amount of overhead.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8964>
 2021-03-04 13:59:20 -08:00
Kenneth Graunke
5659460af4 iris: Defer uploading of surface states 
With u_threaded_context, create_surface and create_sampler_view will
be called from a different thread than the driver thread.  They aren't
allowed to access the context, which means that they can't use the
uploaders there to upload our SURFACE_STATE entries.

Thanks to backing-storage replacement and iris_rebind_buffer, we already
reworked things to maintain CPU-side copies of the SURFACE_STATE entries
and added the ability to upload or re-upload them later.  So we can skip
the upload at object creation time, and add a simple resource-is-NULL
check at binding table upload time to ensure that they get uploaded by
the time we need them.  (They might get uploaded earlier due to rebinds
or clear color updates, but this is the last moment to do so.)

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8964>
 2021-03-04 13:59:20 -08:00
Eric Anholt
3bdd39f03c lima: avoid stomping over bound shader state when creating new shaders 
It shouldn't affect bound program state, and the current context state
shouldn't be relevant for shader creation precompiles anyway (level load
isn't going to have the eventual set of sampler views bound when you go to
draw with that shader).

Closes: #4306
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9089>
 2021-03-04 18:34:35 +00:00
Eric Anholt
4ac3f85054 lima: upload the shader to a BO at shader creation 
No need to conditionally upload later.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9089>
 2021-03-04 18:34:35 +00:00
Eric Anholt
5a550c8dc7 lima: don't look at dirty bits for setup of FS key 
You always have to populate the key with the right texture swizzles, even
if textures haven't changed since binding a new shader.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9089>
 2021-03-04 18:34:35 +00:00
Eric Anholt
d4f706389c lima: stop encoding the texture format in the shader key 
We can compose the swizzles at sampler view creation time, saving
recompiles on texture format changes.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9089>
 2021-03-04 18:34:34 +00:00
Lionel Landwerlin
8023d6de20 anv: implement INTEL_DEBUG=submit 
Name all the BOs!

v2: Fix 32bit build issue (Thanks Marge!)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5736>
 2021-03-04 19:46:24 +02:00
Rohan Garg
c6eb84ff30 virgl: Add support for querying detailed memory info 
This allows for virgl guests to expose GL_NVX_gpu_memory_info and
GL_ATI_meminfo when the extensions are supported on the host.

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9337>
 2021-03-04 17:14:14 +01:00
Jason Ekstrand
1e53e0d2c7 intel/mi_builder: Drop the gen_ prefix 
mi_ is already a unique prefix in Mesa so the gen_ isn't really gaining
us anything except extra characters.  It's possible that MI_ may
conflict a tiny bit with GenXML but it doesn't seem to be a problem
today and we can deal with that in the future if it's ever an issue.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9393>
 2021-03-04 15:14:27 +00:00
Jason Ekstrand
6d522538b6 intel: Rename gen_mi_builder.h to mi_builder.h 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9393>
 2021-03-04 15:14:27 +00:00
Danylo Piliaiev
7e25e5b56f ir3: disallow moving memory writes over discard 
Writes to global memory should not be moved over discard,
otherwise we could have unintended side-effects or lack of
side-effects where they should be observed.

Fixes tests:
 dEQP-VK.rasterization.frag_side_effects.color_at_beginning.kill
 dEQP-VK.rasterization.frag_side_effects.color_at_end.kill

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9365>
 2021-03-04 11:40:58 +00:00
Juan A. Suarez Romero
7b3b8524ef ci: Bump deqp to vk-gl-cts 1.2.5.2 
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9369>
 2021-03-04 11:09:35 +00:00
Danylo Piliaiev
72a9f315db ir3: make mark_kill_path exit early if instr is already seen 
Would bring down its complexity in pathological cases.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9386>
 2021-03-04 10:52:06 +00:00
Danylo Piliaiev
9dbb678f5a ir3: prevent duplication of instruction's dependencies 
Otherwise mark_kill_path() is happy to take exponential time to finish.

It was possible to have such chains:
  ...
 stib.base0 imm[0.000000,0,0x0], ssa_233, ssa_234, false-deps:ssa_231, ssa_231
 stib.base0 imm[0.000000,0,0x0], ssa_237, ssa_238, false-deps:ssa_235, ssa_235
 stib.base0 imm[0.000000,0,0x0], ssa_241, ssa_242, false-deps:ssa_239, ssa_239
 stib.base0 imm[0.000000,0,0x0], ssa_245, ssa_246, false-deps:ssa_243, ssa_243
 stib.base0 imm[0.000000,0,0x0], ssa_249, ssa_250, false-deps:ssa_247, ssa_247
 stib.base0 imm[0.000000,0,0x0], ssa_105, ssa_253, false-deps:ssa_251, ssa_251
 stib.base0 imm[0.000000,0,0x0], ssa_109, ssa_256, false-deps:ssa_254, ssa_254
 stib.base0 imm[0.000000,0,0x0], ssa_113, ssa_259, false-deps:ssa_257, ssa_257
 stib.base0 imm[0.000000,0,0x0], ssa_117, ssa_262, false-deps:ssa_260, ssa_260
 stib.base0 imm[0.000000,0,0x0], ssa_265, ssa_266, false-deps:ssa_263, ssa_263
 stib.base0 imm[0.000000,0,0x0], ssa_269, ssa_270, false-deps:ssa_267, ssa_267
 stib.base0 imm[0.000000,0,0x0], ssa_273, ssa_274, false-deps:ssa_271, ssa_271
  ...

Fixes tests:
 dEQP-VK.geometry.layered.cube_array.36_36_12.secondary_cmd_buffer_inherit_framebuffer
 dEQP-VK.geometry.layered.3d.64_64_8.secondary_cmd_buffer_inherit_framebuffer
 dEQP-VK.geometry.layered.cube_array.64_64_12.secondary_cmd_buffer_inherit_framebuffer

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9386>
 2021-03-04 10:52:06 +00:00
Samuel Pitoiset
517600b4d5 Revert "radv: stop using VM_ALWAYS_VALID on APUs" 
Disabling VM_ALWAYS_VALID actually hurts more than it helps
after doing more testing. Managing the global BO list in userspace
is really costly and make a bunch of games CPU bound.

I think re-enabling VM_ALWAYS_VALID is a step in the right direction.

This reverts commit 6ac6e2fbfb.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9341>
 2021-03-04 09:37:59 +00:00
Gert Wollny
e148d5ec99 r600/sfn: lower intrinsic_load_tess_coord to driver version 
Fixes
  KHR-GL45.tessellation_shader.tessellation_shader_tessellation.TCS_TES
  KHR-GL45.tessellation_shader.tessellation_shader_tessellation.TES

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9373>
 2021-03-04 09:14:03 +00:00
Gert Wollny
81b41e0c76 nir: Add r600 specific intrinsic for loading the tesselation coords 
Only the XY pair is provided directly, the Z value has to be deducted
from the primitive type.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9373>
 2021-03-04 09:14:03 +00:00
cheyang
6f4c4df6c2 virgl: add astc 2d compressed formats 
Signed-off-by: cheyang <cheyang@bytedance.com>
Signed-off-by: hexin   <hexin.op@bytedance.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9306>
 2021-03-04 09:03:47 +00:00
Iago Toral Quiroga
c3732ac0d0 broadcom/compiler: be more aggressive skipping unifa writes 
We had an optimization in place to skip a unifa write if the address
happens to be right after the last ldunifa read address, but we can
take this further and update the unifa address by emitting ldunifa
instructions if needed to skip a unifa write that is close enough.
This is because a unifa write involves 4 cycles: 1 for the write
and 3 delay slots before we can emit the first ldunifa.

So if we have code like this:

unifa addr + 0
ldunifa.r0
unifa addr + 12
ldunifa.r1

In practice we end up with QPU like this:

unifa addr + 0
nop
nop
nop
ldunifa.r0
unifa addr + 12
nop
nop
nop
ldunifa.r1

And with this patch we get:

unifa addr + 0
nop
nop
nop
ldunifa.r0  <--- reads offset 0
ldunifa.-   <--- reads offset 4
ldunifa.-   <--- reads offset 8
ldunifa.r1  <--- reads offset 12

Of course, QPU scheduling might find ways to fill the NOPs to some
extent and remove some of the gains, but generally speaking, this is
still usually a win.

Going by shader-db results, allowing the next unifa address to be up
to 12 bytes after the address resulting from the last ldunifa read
shows the best results:

total instructions in shared programs: 13817048 -> 13812202 (-0.04%)
instructions in affected programs: 602701 -> 597855 (-0.80%)
helped: 1750
HURT: 760
Instructions are helped.

total uniforms in shared programs: 3795485 -> 3793200 (-0.06%)
uniforms in affected programs: 43930 -> 41645 (-5.20%)
helped: 898
HURT: 0
Uniforms are helped.

total max-temps in shared programs: 2326612 -> 2326621 (<.01%)
max-temps in affected programs: 651 -> 660 (1.38%)
helped: 10
HURT: 21
Inconclusive result (value mean confidence interval includes 0).

total sfu-stalls in shared programs: 30942 -> 30906 (-0.12%)
sfu-stalls in affected programs: 627 -> 591 (-5.74%)
helped: 186
HURT: 158
Inconclusive result (value mean confidence interval includes 0).

total inst-and-stalls in shared programs: 13847990 -> 13843108 (-0.04%)
inst-and-stalls in affected programs: 601404 -> 596522 (-0.81%)
helped: 1747
HURT: 757
Inst-and-stalls are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9384>
 2021-03-04 09:00:15 +01:00
Iago Toral Quiroga
2897a83ff8 broadcom/compiler: drop the destination for unused ldunifa 
We can't remove unused ldunifa that are not the first or last
in a sequence, but we can still ignore their destination
to reduce register pressure.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9384>
 2021-03-04 09:00:15 +01:00
Timothy Arceri
9d1ef1595c util/disk_cache: make MESA_DISK_CACHE_READ_ONLY_FOZ_DBS a relative path 
Rather than passing in full paths this changes things so that we can
just pass in filenames relative to the current cache directory.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9279>
 2021-03-04 04:07:46 +00:00
Eric Anholt
a8423eb732 ci/turnip: Mark a flaky WSI test. 
This one has flaked many times at this point, and I've even seen it flake
locally.  No luck debugging it yet.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9397>
 2021-03-03 23:03:48 +00:00
Rob Clark
f8714b2852 freedreno: Remove dead-cells MBR workaround 
With threaded-context we won't have a chance to apply the workaround in
the backend driver.  But the previous commit moves it to a driconf
configured workaround in mesa/st, so we can drop this now.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9316>
 2021-03-03 22:47:59 +00:00
Rob Clark
e6f2e8b3fc driconf: Add ignore_map_unsynchronized option 
Add an option to workaround incorrect unsynchronized VBO updates in
Dead-Cells.

See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4337
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9316>
 2021-03-03 22:47:59 +00:00
Mike Blumenkrantz
3c20b698e2 zink: rewrite macro for getting KHR device functions 
we have the technology. we can improve our our lives with better macros.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9398>
 2021-03-03 17:27:22 -05:00
Rob Clark
910a2464cf freedreno/a6xx: Fix compile warning 
Fixes: 79921b81bc ("freedreno/a6xx: Document threadsize-related fields")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9394>
 2021-03-03 22:09:22 +00:00
Rob Clark
8642456472 freedreno: Deduplicate fixup_shader_state() 
All the ir3 gens had the same thing, time to move it out into a shared
helper.

The keeping the storage in fdN_context is to avoid namespace clashes
between ir3 and ir2.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9394>
 2021-03-03 22:09:22 +00:00
Rob Clark
1611693977 freedreno/ir3: Add comments about shader key/gen 
I had forgotton on which gens these where used on (which is important if
you need to know which shader stages use these).. expand the comments a
bit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9394>
 2021-03-03 22:09:22 +00:00
Dave Airlie
bc02fc4823 clover: fix array images view creation 
Found this on top of Karol's patches but it seems like it can just be
applied to master.

Helps with some cases of
kernel_image_methods/test_kernel_image_methods 2Darray

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9381>
 2021-03-03 21:59:22 +00:00
Eric Anholt
18be15ad16 ci/zink: Add another primitive restart flake. 
This one flaked all the way to a run failure in a recent MR of mine.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9396>
 2021-03-03 21:49:41 +00:00
Eric Anholt
283a05ddc9 ci/a5xx: Update piglit expectations. 
The mesa/st shader variants change fixed some fails for us.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9314>
 2021-03-03 21:05:39 +00:00
Eric Anholt
957132294f ci/a5xx: Increase the gles3/31 coverage. 
Now that there's more time available in our budget per board, we can run
all of gles31, and half of gles3, instead of 10%.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9314>
 2021-03-03 21:05:39 +00:00
Eric Anholt
1087bf16af ci/a3xx: Run all of GLES3 dEQP. 
We're not spending half our time booting any more, so run the other half.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9314>
 2021-03-03 21:05:39 +00:00
Eric Anholt
bb82efa792 ci/a5xx: Run all of gles2 in one job. 
Now that we're not spending so much time on boot overhead, no need to
parallelize.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9314>
 2021-03-03 21:05:39 +00:00
Eric Anholt
bcdfee3bcd ci/freedreno: Switch the fastboot boards to using nfsroot. 
This saves time in packing the rootfs, allows for larger rootfses, and
avoids the need for webdav.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9314>
 2021-03-03 21:05:39 +00:00
Eric Anholt
5c89f6ed17 ci/freedreno: Also retest when only CI configuration changes. 
Fixes: dab845d457 ("ci: Move specific driver testing to separate files in separate dirs.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9314>
 2021-03-03 21:05:39 +00:00
Eric Anholt
e2aff7425d tgsi_exec: Jump over entirely non-taken THEN or ELSE branches. 
TGSI has these nice labels for us for where to jump in this case, let's
use them.  Improves piglit arb_shader_image_load_store-shader-mem-barrier
runtime massively, though not enough to make the test really reasonable to
run.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9347>
 2021-03-03 20:47:08 +00:00
Eric Anholt
3429c83f87 tgsi_exec: Roll the loops for condmask handling. 
No need to hand-unroll this, the compiler will do it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9347>
 2021-03-03 20:47:08 +00:00
Ilia Mirkin
ac6aad3d59 i965: support GL_EXT_color_buffer_half_float 
FP16 rendering is supported on all gen4 hardware.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9379>
 2021-03-03 20:37:03 +00:00
Antonio Caggiano
810c39b067 ci: Use lock file to build deqp-runner 
Build deqp-runner with the `--locked` option to use dependencies
versions specified in `Cargo.lock`.

v2: Bump image tags.

Signed-off-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Suggested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9368>
 2021-03-03 20:21:16 +00:00
Marek Olšák
a0cc0b3a15 ac/llvm: open code fpow on LLVM 12 using fmul.legacy 
A quick look at the asm shows that this enables source modifiers
(neg, abs) for v_mul_legacy_f32.

Totals from affected shaders:
SGPRS: 110104 -> 110400 (0.27 %)
VGPRS: 57632 -> 57636 (0.01 %)
Spilled SGPRs: 66 -> 63 (-4.55 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 3290412 -> 3283068 (-0.22 %) bytes
Max Waves: 32141 -> 32141 (0.00 %)

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9395>
 2021-03-03 20:06:09 +00:00
Marek Olšák
18c1c1404d ac/llvm: add type parameter into ac_build_buffer_load to fix 16-bit TES inputs 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9395>
 2021-03-03 20:06:09 +00:00
Marek Olšák
ed351b9a71 ac/llvm: fix visit_load_ubo_buffer to use SMEM for 16 bits instead of VMEM 
This has 3 advantages:
- It's SMEM.
- Multiple single component loads are merged into 1 multi-dword load by LLVM.
- The result is always packed for packed instructions.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9395>
 2021-03-03 20:06:09 +00:00
Marek Olšák
46ce67a331 ac/llvm: implement 16-bit and 64-bit fpow correctly 
LLVM converts to 32 bits and back for llvm.pow, so we can't use it.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9395>
 2021-03-03 20:06:09 +00:00
Marek Olšák
3475c79328 ac/llvm: add support for 16-bit source operands for samplers 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9395>
 2021-03-03 20:06:09 +00:00
Ian Romanick
c393ae9d84 nir/search: Constify instruction parameter to search helpers 
The search helps must *never* modify the instruction passed in, so let
the compiler enforce this.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9378>
 2021-03-03 18:32:14 +00:00
Lionel Landwerlin
0f437e49c6 anv: fix missing general state pool in validation list 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 83fee30e85 ("anv: allow multiple command buffers in anv_queue_submit")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9388>
 2021-03-03 18:24:16 +00:00
Eric Anholt
f3f4a24549 ci/lava: Move the driver expectation files to the per-driver CI dir. 
This will cause less retesting of other drivers when changing the dEQP
results for a driver.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9353>
 2021-03-03 18:08:11 +00:00
Eric Anholt
9f03ee7773 ci/lava: Move the per-driver gitlab-ci.yml to each driver. 
Follow-up to !9139, will cause less testing of other drivers when changing
the CI configuration for a single driver.

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9353>
 2021-03-03 18:08:11 +00:00
Eric Anholt
27e0181523 ci: Move deqp-default-skips.txt back to .gitlab-ci/ 
Since we don't manually enumerate the drivers using it, we have to retest
all drivers when changing it (which basically never happens, anyway).

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9353>
 2021-03-03 18:08:11 +00:00