Commit Graph

60268 Commits

Author SHA1 Message Date
Alex Deucher
e2d53fac1c r600g: fix SUMO2 pci id
0x9649 is sumo2, not sumo.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
CC: "9.2" "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-24 15:22:31 -05:00
Vinson Lee
35a3414302 scons: Add system library linker flags on LLVM 3.5.
llvn-3.5svn r197664 split out the linker flags from ldflags to
system-libs.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
2013-12-23 11:33:29 -08:00
Aaron Watry
3ddabe0d52 r600/pipe: Stop leaking context->start_compute_cs_cmd.buf on EG/CM
Found while tracking down memory leaks in VDPAU playback

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

CC: "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-23 07:24:50 -06:00
Aaron Watry
20446d0e53 st/vdpau: Destroy context when initialization fails
Prevents a potential memory leak found when tracking down something else.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

CC: "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-23 07:24:50 -06:00
Aaron Watry
767b0f82c3 radeon/llvm: Free target data at end of optimization
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

CC: "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-23 07:24:50 -06:00
Aaron Watry
0bd858d7ff r600/compute: Use the correct FREE macro when deleting compute state
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

CC: "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-23 07:24:50 -06:00
Aaron Watry
e19717d075 r600/compute: Free compiled kernels when deleting compute state
v2: Remove unnecessary null pointer check

CC: "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-23 07:24:50 -06:00
Aaron Watry
8c9a9205d9 radeon/compute: Stop leaking LLVMContexts in radeon_llvm_parse_bitcode
Previously we were creating a new LLVMContext every time that we called
radeon_llvm_parse_bitcode, which caused us to leak the context every time
that we compiled a CL program.

Sadly, we can't dispose of the LLVMContext at the point that it was being
created because evergreen_launch_grid (and possibly the SI equivalent) was
assuming that the context used to compile the kernels was still available.

Now, we'll create a new LLVMContext when creating EG/SI compute state, store
it there, and pass it to all of the places that need it.

The LLVM Context gets destroyed when we delete the EG/SI compute state.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

CC: "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-23 07:24:50 -06:00
Aaron Watry
a7653c19a3 pipe_loader/sw: close dev->lib when initialization fails
Prevents a memory leak.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

CC: "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-23 07:24:50 -06:00
Aaron Watry
862f55c29c clover: Remove unused variable
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

CC: "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-23 07:24:50 -06:00
Jonathan Liu
7990ab58fa llvmpipe: use pipe_sampler_view_release() to avoid segfault
This fixes another case of faulting when freeing a pipe_sampler_view
that belongs to a previously destroyed context.

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jonathan Liu <net147@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-22 07:07:56 -07:00
Jonathan Liu
670be71bd8 st/mesa: use pipe_sampler_view_release()
This fixes a crash where old_view->context was already freed in the
pipe_sampler_view_reference function contained in
src/gallium/auxiliary/utils/u_inlines.h. As a result, the
sampler_view_destroy function pointer contained 0xfeeefeee indicating
freed heap memory.

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jonathan Liu <net147@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-22 07:07:07 -07:00
Henri Verbeet
b094b3b9f4 i915: Add support for gl_FragData[0] reads.
Similar to 556a47a262, without this reading from
gl_FragData[0] would cause a software fallback.

Bugzilla: https://bugs.winehq.org/show_bug.cgi?id=33964
Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
Cc: 10.0 9.2 9.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-22 11:55:39 +01:00
Andreas Hartmetz
2efe7927d3 radeonsi: Use htile_buffer for depth only when there is no stencil.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2013-12-22 01:41:03 +01:00
Niels Ole Salscheider
900ac63ee8 winsys/radeon: remove superfluous distinction of cases
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2013-12-22 01:41:02 +01:00
Mark Mueller
852db050b9 mesa: inline r200 radeon texture format macros to facility search and replace
Signed-off-by: Mark Mueller <MarkKMueller@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2013-12-21 15:27:29 +01:00
Lauri Kasanen
fcefdc9a59 mesa: Fix build to properly check for supported compiler flags
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72708
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Lauri Kasanen <cand@gmx.com>
2013-12-20 17:00:57 -08:00
Ian Romanick
79f268978d mesa: It is not possible to have GLSL < 1.20
This hasn't been possible for a long time.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-20 16:43:08 -08:00
Ian Romanick
4949322462 mesa: Clean up bad code formatting left from previous commit
Also s/_EXT// on enums that are now part of core.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-20 16:43:08 -08:00
Ian Romanick
a92b9e60ab mesa: GL_EXT_packed_depth_stencil is not optional
Every driver supports it.  All current and future Gallium drivers always
support it, and all existing classic drivers support it.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-20 16:43:08 -08:00
Ian Romanick
b66edff435 radeon: Sort list of enabled extensions
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-20 16:43:08 -08:00
Ian Romanick
1bf436e014 r200: Sort list of enabled extensions
Note that ARB_occlusion_query was previously enabled twice.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-20 16:43:08 -08:00
Lauri Kasanen
fe2079c4c0 glx: Simplify __glxGetMscRate, it only needs the screen, not a drawable
Useful in its own right, but also needed for adaptive vsync.

No regressions in the piglit glx-oml-sync-control-getmscrate test.

Signed-off-by: Lauri Kasanen <cand@gmx.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
2013-12-20 16:43:08 -08:00
Keith Packard
6b51113981 dri3: Rename DRI3_MAX_BACK to DRI3_NUM_BACK
It is the maximum number of back buffers, but the name is confusing and is
easily read as the maximum back buffer index. Chage to DRI3_NUM_BACK to make
the intended usage a bit clearer.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-20 16:31:09 -08:00
Keith Packard
547bcc4b57 i965: Set fast color clear mcs_state on newly allocated image miptrees
Just copying code from the dri2 path to set up the fast color clear state.

This also removes a couple of bogus intel_region_reference calls.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-20 16:19:52 -08:00
Keith Packard
c426fb08cf i965: Correct check for re-bound buffer in intel_update_image_buffer
The buffer-object is the persistent thing passed through the loader, so when
updating an image buffer, check to see if it is already bound to the provided
bo. The region, on the other hand, is allocated separately for the miptree,
and so will never be the same as that passed back from the loader.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-20 16:18:37 -08:00
Keith Packard
ca2012a912 dri3: Clean up struct dri3_drawable
Move the depth field up with width and height.

Remove unused previous_time and frames fields.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-20 16:18:11 -08:00
Keith Packard
95b04850d0 dri3: Free resources when drawable is destroyed.
Always nice to clean up after ourselves.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-20 16:17:59 -08:00
Keith Packard
568a27588d dri3: Switch to libxshmfence version 1.1
libxshmfence v1.0 foolishly used 'int32_t *' for the fence type, which
works when the fence is a linux futex. However, version 1.1
changes the exported datatype to 'struct xshmfence *'

Require libxshmfence version 1.1 and switch the API around.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-20 16:17:54 -08:00
Kenneth Graunke
9f330481c3 i965: Use RED for depth texture formats rather than INTENSITY.
While looking through the documentation, I found this in the Sandybridge
PRM (Volume 4, Part 1, Page 140):
"Use of sample_c with SURFTYPE_CUBE surfaces is undefined with the
 following surface formats: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM,
 I32_FLOAT, L32_FLOAT, A32_FLOAT."

I haven't observed this to be true, but it suggests that we may want to
use other formats.

We already perform DEPTH_TEXTURE_MODE swizzling in the shaders, and
don't rely on the surface format to splat things appropriately.  So
using RED should work just as well as INTENSITY.

A few notes about the formats:
- R24_UNORM_X8_TYPELESS has the exact same properties as I24X8_UNORM.
- R16_UNORM and R32_FLOAT are additionally supported as a render target,
  while the old I16_UNORM/I32_FLOAT formats are not.
- R32_FLOAT_X8X24_TYPELESS is not supported as a render target, while
  the old format (R32G32_FLOAT) was.  However, it shares the same
  properties as the formats we use for Z24, so it should suffice.

This makes translate_tex_format and brw_blorp_surface_info::set
a bit more similar.

No Piglit changes on Sandybridge or Ivybridge.  No oglconform changes on
Sandybridge.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-12-20 16:14:35 -08:00
Chad Versace
1a928816a1 i965/gen6: Fix HiZ hang in WebGL Google Maps
Emitting flushes before depth and hiz resolves at the top of blorp's
state emission fixes the hang. Marchesin and I found the fix
experimentally, as opposed to adhering to a documented hardware
workaround.  A more minimal fix likely exists, but this gets the job
done.

Fixes HiZ hangs in the new WebGL Google maps on Sandybridge Chrome OS.
Tested by zooming in and out continuously for 2 hours.

This patch is based on
8bc07bb701

CC: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70740
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-12-20 15:20:30 -08:00
Kenneth Graunke
b97fa1e75b i965: Store QPitch in intel_mipmap_tree.
Broadwell allows us to specify an arbitrary value for QPitch, rather
than baking a specific formula into the hardware and requiring software
to lay things out to match.  The only restriction is that the software
provided QPitch needs to be large enough so successive array slices do
not overlap.

In order to support this flexibility, software needs to specify QPitch
in a bunch of packets.  Storing QPitch makes that easy, and allows us to
adjust it in a single place should we wish to change it in the future.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-20 12:41:54 -08:00
Kenneth Graunke
1e8e17ccd7 i965: Add support for Broadwell's new register types.
Broadwell introduces support for Q, UQ, and HF types.  It also extends
DF support to allow immediate values.

Irritatingly, although HF and DF both support immediates, they're
represented by a different value depending on the register file.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-20 12:34:43 -08:00
Kenneth Graunke
15b9aa22d7 i965: Add BRW_REGISTER_TYPE_DF.
Ivybridge, Baytrail, and Haswell support double float register types,
but do not support them as immediate values.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-20 12:34:41 -08:00
Kenneth Graunke
54e91e7420 i965: Abstract BRW_REGISTER_TYPE_* into an enum with unique values.
On released hardware, values 4-6 are overloaded.  For normal registers,
they mean UB/B/DF.  But for immediates, they mean UV/VF/V.

Previously, we just created #defines for each name, reusing the same
value.  This meant we could directly splat the brw_reg::type field into
the assembly encoding, which was fairly nice, and worked well.

Unfortunately, Broadwell makes this infeasible: the HF and DF types are
represented as different numeric values depending on whether the
source register is an immediate or not.

To preserve sanity, I decided to simply convert BRW_REGISTER_TYPE_* to
an abstract enum that has a unique value for each register type, and
write translation functions.  One nice benefit is that we can add
assertions about register files and generations.

I've chosen not to convert brw_reg::type to the enum, since converting
it caused a lot of trouble due to C++ enum rules (even though it's
defined in an extern "C" block...).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-20 12:34:39 -08:00
Kenneth Graunke
13454fc3de i965: Decode three-source register types directly.
Three-source instructions use a different encoding for register types
(and have a much more limited set to choose from).

Previously, we translated those into BRW_REGISTER_TYPE_* values, then
reused the existing reg_encoding mapping.

Doing it directly is more straightforward and actually less code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-20 12:34:38 -08:00
Kenneth Graunke
4e95a09937 i965: Disassemble UV types, not UB types.
UB types have never been supported as immediates.  On Gen4-5, register
encoding 4 is "Reserved."  On Gen6+, it means UV.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-20 12:34:36 -08:00
Kenneth Graunke
d10242c5f7 i965: Add missing BRW_REGISTER_TYPE_UV.
Sandybridge added support for packed unsigned vectors.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-20 12:34:15 -08:00
Kenneth Graunke
51c9cfc296 i965: Fix 3DSTATE_PUSH_CONSTANT_ALLOC_PS packet creation.
When adding geometry shader support, we accidentally reversed the size
and offset parameters.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-20 12:25:43 -08:00
Kenneth Graunke
0d0edf8e4c i965: Use {point_sprite,flat}_enable variable names instead of dw*.
Calling the local variables flat_enable and point_sprite_enable is
clearer than dw16 and such.  It also matches the names used in
calculate_attr_overrides, which computes them.

v2: Add /* dw16 */ and /* dw10 */ comments, requested by Jordan.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2013-12-20 12:25:33 -08:00
Kenneth Graunke
23fc845f81 i965: Zero out {point_sprite,flat}_enables in calculate_attr_overrides.
calculate_attr_overrides is responsible for computing the point sprite
and flat-shading enable bitfields.  It does so by OR'ing in a bunch of
bits.  However, it relied on the caller to set the initial value to
zero.  This is pretty fragile - if the caller neglects to zero out those
variables, then the enable bitfields end up full of garbage, which shows
up as random things being flat-shaded.

This patch moves the zero-initialization into calculate_attr_overrides,
so that the computation is completely in one place.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2013-12-20 12:25:33 -08:00
Kenneth Graunke
da872ddcc6 i965: Delete bogus BRW_REGISTER_TYPE_HF define.
git blame ascribes this to the initial commit of the driver.

No released hardware has ever supported half float, according to the
documentation for SrcType in the ISA reference.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-12-20 12:25:33 -08:00
Kevin Rogovin
3b1195f8a6 Report that no function found if signature lookup is empty
If no function signature is found for a function name, report that the
function is not found instead of printing an empty list of candidates.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-12-20 09:03:54 -08:00
Kevin Rogovin
23d294bb60 Use line number information from entire function expression
This patch changes the error reporting behavior for incorrect function
invocation (triggered by match_function_by_name() unable to find a
matching function call) from using the line number information
associated to the function name term to using the line number
information of the entire function expression. Fixes bug #72264.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72264
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
2013-12-20 09:03:54 -08:00
Michel Dänzer
d580905000 radeonsi: Only scan pixel shaders for TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
It's not relevant for other shader types.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-12-20 18:51:09 +09:00
Aaron Watry
8252847b7b r600g: Fix spelling error
Trivial change, testing commit access
2013-12-19 14:30:51 -06:00
Quanxian Wang
1413a09f34 egl: break instead of looping after driver is found
Stop searching for a driver after success.

Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
Reviewed-By: Gong, Zhigang <zhigang.gong@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-19 12:44:11 -07:00
Juha-Pekka Heikkila
22bf0f3eb4 mesa: Assert variable coming from get_variable() in get_current_attrib
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-19 08:26:17 -07:00
Juha-Pekka Heikkila
a7d8607d9e mesa: Add asserts into emit_fog_instructions
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-19 08:25:58 -07:00
Juha-Pekka Heikkila
cd6aaf2920 glx: Fix two identical null check errors in driSet/GetInterval
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2013-12-19 08:25:45 -07:00