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Author SHA1 Message Date
Lionel Landwerlin
80a352c87c anv: remove aux checking asserts 
Zink is running into those asserts on CI. The problem is that with non
auxilary modifiers like I915_FORMAT_MOD_Y_TILED, we might still
allocate larger buffers with IMPLICIT_CCS.

This isn't a complete fix, the real fix with come with
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25003 where
we stop overallocating and those assert will match the private binding
allocation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 569f80f2df ("anv: Reduce accesses of isl_mod_info->aux_usage")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25099>
 2023-09-08 16:57:53 +00:00
Samuel Pitoiset
64a5472ad7 radv: remove useless PIPELINE_CREATE_2_LIBRARY_BIT check for retained shaders 
VK_PIPELINE_CREATE_2_RETAIN_LINK_TIME_OPTIMIZATION_INFO_BIT_EXT is only
allowed for pipeline libs, so VK_PIPELINE_CREATE_2_LIBRARY_BIT_KHR
should also be set.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25110>
 2023-09-08 16:26:40 +00:00
David Rosca
d6299ec258 frontends/va: Flush after unmapping VAImageBufferType 
If application changed image data we need to flush on unmap to make the
changes visible. This will also flush if the mapping was used only for
reading, but we can't know that as vaMapBuffer doesn't have a parameter
to specify if read or write is requested.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9774

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25102>
 2023-09-08 16:07:34 +00:00
Georg Lehmann
136a698251 nir/opt_algebraic: remove broken fddx/fddy patterns 
These patterns are broken in the following scenario:

%1 = f2fmp %0
%2 = fddx %1
%3 = ... // non quad uniform
if %3 {
   %4 = f2f32 %2
   ...
}

Which would turn into

%3 = ...
if %3 {
   %4 = fddx %0
   ...
}

Yet another example that shows why derivative instructions should be
be intrinsics, not alu.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25014>
 2023-09-08 14:14:47 +00:00
Dave Airlie
109a99e691 llvmpipe: enable f16 paths on aarch64. 
Karol noticed luxmark didn't work, and this seems to fix it.

Cc: mesa-stable
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25104>
 2023-09-08 13:18:51 +00:00
Samuel Pitoiset
adaf4460bd radv: do not use pre-compiled prologs when VS is compiled separately 
This wouldn't work for VS+TCS or VS+GS if they are compiled separately
on GFX9+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24933>
 2023-09-08 12:43:29 +00:00
Samuel Pitoiset
871a383671 radv: adjust emitted prolog regs for merged shaders compiled separately 
It should also be the merged shader stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24933>
 2023-09-08 12:43:28 +00:00
Samuel Pitoiset
657cabe17e radv: adjust next stage for VS prologs and merged shaders compiled separately 
It should be the merged shader stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24933>
 2023-09-08 12:43:28 +00:00
Georg Lehmann
524a894ba4 aco/gfx11: don't use bfe for local_invocation_id if the others are always 0 
Foz-DB GFX1100:
Totals from 4469 (3.37% of 132657) affected shaders:
Instrs: 3895053 -> 3893529 (-0.04%); split: -0.04%, +0.00%
CodeSize: 20244128 -> 20220952 (-0.11%); split: -0.11%, +0.00%
Latency: 37864147 -> 37862227 (-0.01%); split: -0.01%, +0.00%
InvThroughput: 5578100 -> 5576469 (-0.03%); split: -0.03%, +0.00%
SClause: 108336 -> 108343 (+0.01%); split: -0.00%, +0.01%
Copies: 275897 -> 275900 (+0.00%); split: -0.00%, +0.00%

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24514>
 2023-09-08 11:28:24 +00:00
Danylo Piliaiev
1409f69e00 tu: Call tu_cs_dbg_stomp_regs with appropriate GPU gen 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25098>
 2023-09-08 09:58:07 +00:00
Danylo Piliaiev
cb08ccb378 tu: Exclude SP_UNKNOWN_AE73 from reg stomping 
There is a guess that GPU may not be able to handle different values of
certain debug register between BR/BV. This one causes GPU to hang.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25098>
 2023-09-08 09:58:06 +00:00
Pierre-Eric Pelloux-Prayer
84e61d606b radv/sdma: use correct limits for gfx10.3 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24771>
 2023-09-08 09:15:20 +00:00
Pierre-Eric Pelloux-Prayer
c707cb51e5 radv/sdma: use multiple commands if required 
Instead of failing the copy we can use multiple chunks.

This codepath shouldn't really be used since the source
image should usually be tiled but it still better to not
fail when possible.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24771>
 2023-09-08 09:15:20 +00:00
Pierre-Eric Pelloux-Prayer
ca25d5f846 radeonsi/sdma: use multiple commands if required 
Instead of failing the copy we can use multiple chunks.

This codepath shouldn't really be used since the source
image should usually be tiled but it still better to not
fail when possible.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24771>
 2023-09-08 09:15:20 +00:00
Eric Engestrom
a69ffbd08a ci: taking igalia farm offline 
We're having internet issues, everything is extremely slow.
 2023-09-08 09:37:52 +01:00
Timothy Arceri
84e0f5ce75 nir: remove unused param from nir_alu_src_copy() 
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24986>
 2023-09-08 03:01:39 +00:00
Timothy Arceri
9b6eae2e67 nir: remove unused nir_src_copy() 
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24986>
 2023-09-08 03:01:39 +00:00
Timothy Arceri
af1528cc15 nir: replace use of nir_src_copy() 
Since 03b2c34793 nir_src_copy() no longer does anything useful,
it will be removed in the following patch.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24986>
 2023-09-08 03:01:39 +00:00
Mike Blumenkrantz
fd297ecf98 zink: always add a per-prog ref for gpl libs 
previously non-separable progs had their libs owned exclusively by
the shaders, which meant it was possible for a background compile job
to crash while the context was being destroyed when accessing libs
which no longer had active shaders

fixes #9234

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25088>
 2023-09-08 01:35:00 +00:00
Bas Nieuwenhuizen
4303ea7b9a radv: Use a double jump to limit nops in DGC for dynamic sequence count. 
Some RGP data showing that a large amount of NOPs might be a performance
concern.

Some data from a Granite demo repurposed as benchmark:
  - with max_count = 16, actual draw count 1-4, the new path is ~5% slower
  - with max_count = 2048, actual draw count 1-4, the new path is >2x as fast.
  - with max_count = 16384, actual draw count 1-4, the new path is >7x as fast.

Due to the new path being slower in e.g. small cmdbuffers I added a heuristic.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25046>
 2023-09-08 00:41:34 +00:00
David Heidelberg
05bd55a994 ci/traces: extend no-output timeout by 5 minutes 
This should help us handling possibly slower downloads of the traces,
which leads into piglit not printing anything on the output.

After Infra will get stabilized again, needs to be reverted.

Acked-by: Helen Koike <helen.koike@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25097>
 2023-09-07 23:43:02 +00:00
Samuel Pitoiset
a2ead228ac radv: avoid emitting THREAD_TRACE_MARKER for predicated draws/dispatches 
This confused RGP for example when DGC calls are skipped.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25060>
 2023-09-07 22:51:51 +00:00
Samuel Pitoiset
51eb072eb6 radv: skip DGC calls when the indirect sequence count is zero with a predicate 
Starfield has a lot of empty ExecuteIndirect() calls. This optimizes
them by using the indirect sequence count as predicate.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25060>
 2023-09-07 22:51:51 +00:00
Martin Roukala (né Peres)
13723e3097 radv/ci: use the default kernel on vkcts-navi10 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7888
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25095>
 2023-09-07 21:02:25 +00:00
Martin Roukala (né Peres)
76ef5f82ab radv/ci: drop the auto-reboot-on-hang for vkcts-navi10 
Anecdotal evidence seems to suggest this is not happening anymore, so
let's try dropping it and see how it fares!

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25095>
 2023-09-07 21:02:25 +00:00
Danylo Piliaiev
b16472fc97 ir3/lower_tex_prefetch: Fix crash with lowered load_barycentric_at_offset 
ir3_nir_lower_tex_prefetch expects src0 of load_interpolated_input to
be intrinsic, however this assumption broke when src0 is
load_barycentric_at_offset and is lowered in series of alu instructions.

 32x2  %1121 = @load_barycentric_at_offset (%1120) (interp_mode=0)
 32x4  %1118 = @load_interpolated_input (%1121, %1116 (0x0)) ...
 32x2    %32 = vec2 %1118.x, %1118.y
 32x4    %37 = (float32)tex %36 (texture_handle), %34 (sampler_handle), %32 (coord), 0 (texture), 0 (sampler)

is lowered into:

 [...]
 32      %54 = ffma %46.y, %52, %50
 32      %55 = ffma %46.y, %53, %51
 32x2    %56 = vec2 %54, %55
 32x4    %57 = @load_interpolated_input (%56, %25 (0x0))
 [...]

Crash backtrace:

 #5  in __GI___assert_fail (assertion=0x7ff6692328 "parent && parent->type == nir_instr_type_intrinsic",
     file=0x7ff66921c8 "nir.h", line=2536, function=0x7ff6692630 <__PRETTY_FUNCTION__.13> "nir_instr_as_intrinsic")
     at assert.c:101
 #6  in nir_instr_as_intrinsic (parent=0x7fd4b648e8) at nir.h:2536
 #7  in coord_offset (ssa=0x7fd4b649d0) at ir3_nir_lower_tex_prefetch.c:77
 #8  in coord_offset (ssa=0x7fd4b64a90) at ir3_nir_lower_tex_prefetch.c:48
 #9  in ir3_nir_coord_offset (ssa=0x7fd4b64a90) at ir3_nir_lower_tex_prefetch.c:104
 #10 in lower_tex_prefetch_block (block=0x7fd482c100) at ir3_nir_lower_tex_prefetch.c:185
 #11 in lower_tex_prefetch_func (impl=0x7fd4aa0890) at ir3_nir_lower_tex_prefetch.c:218
 #12 in ir3_nir_lower_tex_prefetch (shader=0x7fd4942b10) at ir3_nir_lower_tex_prefetch.c:242

Cc: mesa-stable

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25096>
 2023-09-07 16:12:58 +00:00
Iago Toral Quiroga
eb7a46ed3d v3dv: bump up MAX_UNIFORM_BUFFERS to 16 
We currently expose 12 but that becomes 11 when running on Zink
since Mesa's state tracker is aware that the first one is reserved
for its own constant buffer, and the minimum number of UBOs required
by GL is 12, so Zink won't be able to expose UBO support.

Bump it up to 16 to meet Zink requirements, which is what we offer
on V3D.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9764
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25093>
 2023-09-07 12:46:10 +00:00
Tatsuyuki Ishi
383842fab8 radv: Fix dumping vertex descriptors with RADV_DEBUG=hang. 
Adding 3 words should be done before the uint32_t ** cast. This is in
line with other places which uses pointer arithmetic on trace_id_ptr.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25081>
 2023-09-07 11:50:32 +00:00
Vlad Schiller
6d2d74fa1c pvr: Add VK_KHR_driver_properties 
This commit will implement the VK_KHR_driver_properties extension.
At the moment, the extension is disabled, because the current conformance
test version does not include the Imagination driver ID. The extension
can be enabled after conformance test version 1.3.6.0.

Co-Authored-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24927>
 2023-09-07 11:35:05 +00:00
Lionel Landwerlin
34813e13db pps-producer: add ability to select device with DRI_PRIME 
When running with multiple Intel cards in a system, having the ability
to select the device recording performance data is useful.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25051>
 2023-09-07 10:44:51 +00:00
Tatsuyuki Ishi
0228b294e8 radv: Fix IB size for RADV_DEBUG=hang. 
cs->base.cdw here is the size of the last CS in the chain, but we are
passing in the first CS in the chain to begin decoding. Hence,
cs->ib_buffers[0].cdw is the correct size here.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25061>
 2023-09-07 09:45:19 +00:00
Tapani Pälli
6e4663635f mesa: disable snorm readpix clamping with EXT_render_snorm 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25054>
 2023-09-07 08:59:07 +00:00
Samuel Pitoiset
285223d0fd radv: fix interactions with primitives generated queries and pipeline stats 
SAMPLE_STREAMOUTSTATS requires PIPELINESTAT_START to be enabled,
otherwise the hw doesn't count anything.

This fixes
dEQP-VK.transform_feedback.primitives_generated_query.concurrent.pipeline_statistics_2.*
on GFX8. GFX6-9 are probably also affected by this bug, but with NGG
these queries are slightly different and don't use legacy streamout.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25049>
 2023-09-07 08:06:40 +00:00
Lionel Landwerlin
6f4fe3f81b anv: Copy/Clear MSAA images over companion RCS while we are on compute 
When we have MSAA copy/clear operation on the compute queue, use the
companion RCS command buffer to carry out copy/clear operations.

v2: (Sagar)
- Flush cache according to command buffer
- Invalidate AUX when we create new companion RCS command buffer if
  platform support AUX TT.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge
5b8bef8650 anv: Extract batch print code to anv_print_batch helper 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge
9866c4e32b anv: Skip layout transition on the compute queue 
v2: (Nanley)
- Make sure we skip layout transition during queue ownership transfer

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge
46d203c0ab anv: Add secondary companion RCS cmd buffer to primary 
Add secondary buffer's companion RCS command buffer to primary buffer's
companion RCS command buffer for execution if secondary RCS is valid.

v2: (Lionel)
- Fix the primary companion RCS check
- Set batch error

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge
4d79c2d280 anv: Execute an empty batch to sync main and companion RCS batch 
We need to synchronize main (CCS/BCS) and companion rcs batch, so let's
create an empty batch and make both the batches (CCS/BCS) and companion
RCS batch wait on empty sync batch and signal the fence.

Reason to execute the empty batch is we need to make sure the companion
RCS batch finish as soon as the CCS/BCS batch finish. Preemption could
prevent the companion RCS batch execution and we might end up destroying
the CCS/BCS batch before companion RCS finishes.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge
0c49d3cf97 anv: Setup companion RCS command buffer submission 
Add all the wait fences from the main (CCS/BCS) command buffer to the
companion RCS command buffer so that the companion RCS batch starts at
the same time as the main (CCS/BCS) batch.

v2:
- Drop unncessary flush (Jose)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge
a63277ec36 anv: Execute RCS init batch on companion RCS context/engine 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge
103512ef3b anv: Move compute specfic bits under compute queue init 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge
b375302576 anv: Create companion RCS engine 
We need to create companion RCS engine when there is CCS/BCS engine
creation requested.

v2:
- Factor out anv_xe_create_engine code in create_engine (Jose)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Lionel Landwerlin
a5f2c8c845 anv: create individual logical engines on i915 when possible 
This enables us to create more logical engines than HW engines are
available. This also brings the uAPI usage closer to what is happening
on Xe.

Rework: (Sagar)
- Correct exec_flag at the time of submission
- Handle device status check
- Set queue parameters

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge
a5e4be45c0 intel: Pass virtual memory address space ID while creating context 
In future patches, we will be creating a separate companion RCS engine
and each engine is created with it's own address space, and we really
don't want. CCS and RCS engine writes should be visible to each other in
order to get the wait/signal mechanism working.

v2:
- Move drm_i915_gem_context_create_ext_setparam out of if block (Lionel)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge
b73960fc40 intel: Add helper to create/destroy i915 VM 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge
13b3d7f741 anv: Handle companion RCS in end/destory/reset code path 
If we have valid companion RCS command buffer, we should
end/destroy/reset in the same fashion as of main command buffer.

v2:
- Add lock around anv_cmd_buffer_destroy (Sagar)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:06 +00:00
Sagar Ghuge
801523f03d anv: Split out End/Destroy/Reset cmd buffer code into helper 
Since we are going to have companion RCS command buffer, we need to
end/destroy/reset companion RCS command buffer similar to main (CCS/BCS)
command buffer.

It's better to split out common code into helper function so that we can
use it later in this series.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:05 +00:00
Sagar Ghuge
edcde0679c anv: Add helper to create companion RCS command buffer 
This helper takes the main command buffer as input and then create a
companion RCS command buffer.

v2:
- Rename anv_get_render_queue_index helper to
  anv_get_first_render_queue_index (Jose)
- Rename RCS command buffer to companion RCS command buffer (Lionel)
- Add early return in anv_get_first_render_queue_index (Lionel)
- Add lock around the function (Jose)
- Move companion rcs command pool creation in device create (Sagar)
- Reset companion RCS cmd buffer (Sagar)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
 2023-09-07 06:39:05 +00:00
Iago Toral Quiroga
31eaeb8274 v3dv: handle pPlaneLayouts in VkImageDrmFormatModifierExplicitCreateInfoEXT 
We have been ignoring these completely until now. V3D isn't very flexible
regarding image layouts anyway, so for the most part we require that
whatever the user puts here matches exactly what the driver would compute
while setting up the slices. The only exceptions are plane offsets which
and array strides.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9742
Tested-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25074>
 2023-09-07 06:22:36 +00:00
Iago Toral Quiroga
717fbda536 v3dv: be more precise in vkGetImageSubresourceLayout 
Only return non-zero values for arrayPitch and depthPitch if
they make sense for the image type.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25074>
 2023-09-07 06:22:36 +00:00