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Author SHA1 Message Date
Mauro Rossi
ef6725a5f4 hasvk/android: remove numFds check 
Change required for compatibility with minigbm gralloc4
due to gralloc handle having DRV_MAX_FDS = (DRV_MAX_PLANES + 1)

https://android.googlesource.com/platform/external/minigbm/+/refs/tags/android-13.0.0_r18/cros_gralloc/cros_gralloc_handle.h#14

Cc: "22.3" mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7807
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20231>
 2023-08-24 11:07:12 +00:00
Mauro Rossi
143d417fcc anv/android: remove numFds check 
Change required for compatibility with minigbm gralloc4
due to gralloc handle having DRV_MAX_FDS = (DRV_MAX_PLANES + 1)

https://android.googlesource.com/platform/external/minigbm/+/refs/tags/android-13.0.0_r18/cros_gralloc/cros_gralloc_handle.h#14

Cc: "22.2" "22.3" mesa-stable
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20231>
 2023-08-24 11:07:12 +00:00
Chris Spencer
6a4e9b55e4 anv: Don't reject Android image format if external props not supplied 
anv_GetPhysicalDeviceImageFormatProperties2 returns 'not supported' if an
Android hardware buffer external memory handle type is specified, but no
external image format properties output struct is supplied. This struct is
optional, so we should populate it if present, but return successfully
either way.

This fixes an error when using ANV with hwui, which otherwise prevents the
system from booting.[1]

[1] https://cs.android.com/android/platform/superproject/main/+/main:frameworks/base/libs/hwui/renderthread/VulkanSurface.cpp;l=271;drc=ad3fb95aa2fe0be59d3e991ddc883592ab5542bc

Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24844>
 2023-08-24 10:26:09 +00:00
Simon Ser
5ceba97c2e vulkan/wsi/wayland: add support for IMMEDIATE 
Use the tearing-control-unstable-v1 protocol to indicate to the
Wayland compositor that tearing is acceptable.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18268>
 2023-08-24 09:38:54 +00:00
Simon Ser
f7da5e3e38 wayland: enable use of wayland-protocols as a subproject 
This allows developers to link subprojects/wayland-protocols/ to
a repository checkout. Useful when adding support for new protocols.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18268>
 2023-08-24 09:38:53 +00:00
Jordan Justen
d65b0b0424 intel/dev: Add more RPL PCI IDs 
Ref: https://patchwork.freedesktop.org/patch/553646/?series=122712&rev=1
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24820>
 2023-08-24 00:42:19 -07:00
Jordan Justen
27f6b4b1c6 intel/dev: Use RPL-U name on RPL-U devices 
Ref: https://patchwork.freedesktop.org/patch/553646/?series=122712&rev=1
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24820>
 2023-08-24 00:42:19 -07:00
Samuel Pitoiset
112b393766 radv: stop declaring unused SGPR arguments for PS epilogs 
ACO no longer requires these arguments.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24838>
 2023-08-24 07:21:58 +00:00
Samuel Pitoiset
0004d903d4 radv: fix the per-patch data offset when TES isn't linked with TCS 
When TCS and TES aren't linked together and TCS exports unused outputs,
the per-patch data offset needs to be adjusted. This is similar to the
LS-HS vertex stride when VS and TCS aren't linked together.

This fixes a bunch of failures by forcing the driver to use TCS epilogs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24776>
 2023-08-24 06:03:12 +00:00
Tapani Pälli
d65fe6eff1 mesa: fix some TexParameter and SamplerParameter cases 
EXT extension was added without tests so these functions did
not work properly.

Fixes: 799710be88 ("mesa: Add EXT_texture_mirror_clamp_to_edge to extension table")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24845>
 2023-08-24 04:26:52 +00:00
Yonggang Luo
26c5200acf compiler/glsl: Move glsl_print_type from glsl_types.* to ir_print_visitor.cpp 
glsl_print_type only referenced in ir_print_visitor.cpp
there is no need expose it

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24824>
 2023-08-24 02:54:09 +00:00
Yonggang Luo
01ddb18427 compiler: use 4 instead ATOMIC_COUNTER_SIZE in glsl_types.h to avoid #include "mesa/main/config.h" 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24824>
 2023-08-24 02:54:09 +00:00
Yonggang Luo
26a23a7c1f d3d12: replace use of MAX_VERTEX_STREAMS with PIPE_MAX_VERTEX_STREAMS 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24824>
 2023-08-24 02:54:09 +00:00
Yonggang Luo
0b84e38684 intel/brw: use 4 instead of MAX_VERTEX_STREAMS to avoid #include "mesa/main/config.h" 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24824>
 2023-08-24 02:54:08 +00:00
Yonggang Luo
d6f8bdcb5f sfn: Use 4 instead of ATOMIC_COUNTER_SIZE 
../../src/gallium/drivers/r600/sfn/sfn_nir.cpp:458:59: error: ‘ATOMIC_COUNTER_SIZE’ was not declared in this scope

../../src/gallium/drivers/r600/sfn/sfn_shader.cpp:609:53: error: ‘ATOMIC_COUNTER_SIZE’ was not declared in this scope

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24824>
 2023-08-24 02:54:08 +00:00
Rob Clark
75789e9429 tu: Workaround bionic _SC_LEVEL1_DCACHE_LINESIZE 
Bionic just returns a hard-coded 0, which isn't helpful.  But
fortunately on aarch64 it is easy enough just to read the value
ourselves.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24829>
 2023-08-23 22:41:55 +00:00
Kenneth Graunke
08fc4603dd intel/fs: Dump IR for pre-RA scheduler modes in DEBUG_OPTIMIZER 
This lets us more easily compare and contrast the various scheduling
options that the compiler considered.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24707>
 2023-08-23 21:34:38 +00:00
Kenneth Graunke
07f2ad32e4 intel/fs: Pick the lowest register pressure schedule when spilling 
We try various pre-RA scheduler modes and see if any of them allow
us to register allocate without spilling.  If all of them spill,
however, we left it on the last mode: LIFO.  This is unfortunately
sometimes significantly worse than other modes (such as "none").

This patch makes us instead select the pre-RA scheduling mode that
gives the lowest register pressure estimate, if none of them manage
to avoid spilling.  The hope is that this scheduling will spill the
least out of all of them.

fossil-db stats (on Alchemist) speak for themselves:

    Totals:
    Instrs: 197297092 -> 195326552 (-1.00%); split: -1.02%, +0.03%
    Cycles: 14291286956 -> 14303502596 (+0.09%); split: -0.55%, +0.64%
    Spill count: 190886 -> 129204 (-32.31%); split: -33.01%, +0.70%
    Fill count: 361408 -> 225038 (-37.73%); split: -39.17%, +1.43%
    Scratch Memory Size: 12935168 -> 10868736 (-15.98%); split: -16.08%, +0.10%

    Totals from 1791 (0.27% of 668386) affected shaders:
    Instrs: 7628929 -> 5658389 (-25.83%); split: -26.50%, +0.67%
    Cycles: 719326691 -> 731542331 (+1.70%); split: -10.95%, +12.65%
    Spill count: 110627 -> 48945 (-55.76%); split: -56.96%, +1.20%
    Fill count: 221560 -> 85190 (-61.55%); split: -63.89%, +2.34%
    Scratch Memory Size: 4471808 -> 2405376 (-46.21%); split: -46.51%, +0.30%

Improves performance when using XeSS in Cyberpunk 2077 by 90% on A770.
Improves performance of Borderlands 3 by 1.54% on A770.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24707>
 2023-08-23 21:34:38 +00:00
Kenneth Graunke
158ac265df intel/fs: Make helpers for saving/restoring instruction order 
This moves a bit of code out of a large function, but also lets us reuse
it a few extra places in the next commit.

I opted to stop using ralloc here since this is short-lived data that
doesn't need to stick around for the rest of the compile, and it's easy
enough to free.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24707>
 2023-08-23 21:34:38 +00:00
Kenneth Graunke
2dd56921c9 intel/fs: Index scheduler mode string table by mode enum 
pre_modes[] is an array with the modes ordered in our desired
preference.  scheduler_mode_name[] was also in that order, and the two
had to be kept in sync.  This is a little silly; we should just have
a mode enum -> string table and look it up via the enum.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24707>
 2023-08-23 21:34:38 +00:00
Kenneth Graunke
7eba19245d intel/compiler: Move SCHEDULE_NONE handling into schedule_instructions() 
I'm going to introduce another call site for this function, and just
handling SCHEDULE_NONE in the scheduler itself makes more sense than
duplicating the logic.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24707>
 2023-08-23 21:34:38 +00:00
Kenneth Graunke
743fd60bea intel/fs: Account for payload GRFs when calculating register pressure 
The register pressure analysis I wrote in 2013 only considered VGRFs,
and not other GRFs, such as payload registers and push constants.  We
need to consider those too, because payload registers definitely occupy
space and add to pressure.

In 2015, Connor already made the scheduler account for this, so the only
real use for this is in shader statistic dumps and optimizer printouts.
But we should make it more accurate.  (We will use it in more places
shortly, a few commits from now.)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24707>
 2023-08-23 21:34:38 +00:00
Rob Clark
4275781896 docs: Followup to !24636 
Update docs to reflect that EGL_ANDROID_blob_cache is now available even
if on-disk caching is disabled.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24853>
 2023-08-23 21:26:08 +00:00
David Rosca
ee1132bd79 Revert "radeonsi/vcn: add an exception of field case for h264 decoding" 
This change causes page faults when playing corrupted video from the
bugreport. The original issue have now been resolved in firmware.

This reverts commit bfce57c7a5.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9210

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24836>
 2023-08-23 20:27:34 +00:00
Georg Lehmann
87d13ee73d aco: combine a | ~b to bfi(b, a, -1) 
Somehow I missed this when writing the a & ~b patch.

Foz-DB Navi21:
Totals from 1591 (1.20% of 132657) affected shaders:
Instrs: 2316379 -> 2315940 (-0.02%)
CodeSize: 12524240 -> 12528724 (+0.04%); split: -0.00%, +0.04%
Latency: 45393195 -> 45389285 (-0.01%); split: -0.01%, +0.00%
InvThroughput: 8658991 -> 8657944 (-0.01%); split: -0.01%, +0.00%
Copies: 135777 -> 135778 (+0.00%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24505>
 2023-08-23 20:06:49 +00:00
Piotr Kocia
27eafbcd4e nir: Remove dead nir_const_value variables 
nir_const_value variables in nir_const_value_for_int and
nor_const_value_for_uint are unused resulting in unnecessary dead code.
The unused-variable warning has been suppressed by the memset following
their declarations.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24851>
 2023-08-23 19:29:19 +00:00
David Heidelberg
74bf80323e panfrost/ci: revert Disable T720 
Tested, it was just some unlucky coincidence it didn't worked, the
device queue is almost empty.

This reverts commit b0f02973d7.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24850>
 2023-08-23 19:05:30 +00:00
Mike Blumenkrantz
56587b24e5 zink: copy some cs shader properties to the program struct 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24835>
 2023-08-23 18:13:55 +00:00
Konstantin Seurer
1f3ffb7fd9 lavapipe: Lock around CSO destroys 
They can race in llvmpipe_register_shader.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9680
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24827>
 2023-08-23 17:49:38 +00:00
Charmaine Lee
04cb346973 svga: fix stride used in vertex declaration 
The stride for each vertex buffer should come from the corresponding
vertex element structure.

Fixes piglit/glretrace regressions running on svga vgpu9 device.

Fixes: 7672545223 ("gallium: move vertex stride to CSO")

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24841>
 2023-08-23 09:37:38 -07:00
Alyssa Rosenzweig
4b84e76951 asahi: Fix shader stage dirtying 
Now this is actually doing what I expect. drawoverhead #1 score more than
doubles (6091->13375).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
bb663b8595 asahi: Dirty the shader stage when the shader changes 
We need to re-emit all descriptors in this case for correctness. Avoids
regressions from the following commit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
581514d925 asahi: Dirty track VBOs + blend const separately 
We're staging everything anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
24238cc507 asahi: Use proper dirty tracking for VBOs 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
0a5ca3f34f asahi: Use finer dirty tracking for blend constant 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
d6ca887f90 asahi: Decouple sysval lowering from uniform assignment 
For merging shader states, we'll need to lower sysvals separately for each
shader but assign uniforms together for the final merged shader. The easiest way
to do that is to decouple the lowering of sysvals to driver uniform reads, from
the assignment of driver uniform reads to actual uniform registers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
17563210d4 asahi: Put unuploaded uniforms on the batch 
Less copying needed this way.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
871d97f7d0 asahi: Extract sampler upload 
Dirty track it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
9fa5dec767 asahi: Add real per-stage dirty flags 
Instead of just using ~0 as a stub todo.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
9a60478966 asahi: Upload a single draw_uniforms per draw 
Not per stage per draw. This is less frequent.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
4717b08f78 asahi: Extract agx_upload_textures 
By uploading textures ahead-of-time, we can upload uniforms ahead-of-time too.
This will also allow some overhead shaving optimizations, I guess.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
0e6cb6d893 asahi: Collapse grid_info 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
b049b1c98f asahi: Split out per-stage sysvals 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
31afce2fa5 asahi: Add sysval tables for each shader stage 
So we can model the descriptors of each shader stage independently, as required
for merged shaders.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
5189bae50c asahi: Move UBO lowering into GL driver 
In Vulkan, UBOs are lowered by nir_lower_explicit_io, and the ubo_base_agx
sysval is unused (since it doesn't handle descriptor sets). That makes the UBO
lowering GL-only and hence belongs with the GL driver rather than the compiler.
This lets us delete the ubo_base_agx sysval.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
1d77fb967d nir,asahi: Remove texture_base_agx 
Doing a descriptor crawl with binding tables requires a real binding table in
the shader, which won't work for VK or merged shader stages in GL. Instead,
let's lower anything that needs a crawl to bindless in the driver, so the
compiler code doesn't need to know anything about descriptor binding models.
That gets rid of the texture_base_agx sysval, which is problematic when there
are multiple descriptor sets worth of textures.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
cd25f753d5 agx: Add helper returning if a descriptor crawl is needed 
For agx_nir_lower_texture to lower to a descriptor crawl, the driver needs to
make sure the address of the descriptor is available. This means a slightly
different code path should be used in the driver. Rather than the drivers
needing to know what exactly will be lowered, add a helper in the same file as
agx_nir_lower_texture that returns whether descriptor-based lowering will be
needed so the driver can act appropriately.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
1e11862753 agx: Do some texture lowering early 
We want to make the implicit txs in operations explicit before lower_bindings so
lower_bindings knows to force bindless.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
6e1bdc1291 asahi: Add missing LOD source for agx_meta's txfs 
These would be inserted by nir_lower_tex anyway, but we shouldn't be relying on
that behaviour for the meta shaders when we can just create the correct thing
from the start.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00
Alyssa Rosenzweig
176484d7f0 agx: Do not fence write-only images 
Reduces fencing significantly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24847>
 2023-08-23 15:06:55 +00:00