Commit Graph

125220 Commits

Author SHA1 Message Date
Eric Anholt
d9f7fce83c ci: Enable NIR validation on a630 GLES2 and VK tests.
We get through GLES2 in 5.5 minutes and the vk subset in 8 minutes, so we
can spare the CPU time on these tests.

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5554>
2020-06-19 14:50:05 -07:00
Eric Anholt
6ee80d8e0c ci: Bump vulkan CTS to 1.2.3.0.
Looks like it fixes some potentially important VK test bugs.  But also, it
fixes the GLES31 SSBO layout tests to not be so excessively large, so we
can run them in a reasonable time now.  Note that a630 fail list is reset,
since the test list has changed and so we end up with a different subset
of tests being run.  Interestingly, in the process the semaphore tests are
now reporting "NotSupported (Exporting and importing semaphore type not
supported at vktSynchronizationSignalOrderTests.cpp:513)" where they
weren't before.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5554>
2020-06-19 14:50:05 -07:00
Nanley Chery
f8961ea086 iris: Disable sRGB fast-clears for non-0/1 values
For texturing and draw calls, HW expects the clear color to be in two
different color spaces after sRGB fast-clears - sRGB in the former and
linear in the latter. Up until now, iris has stored the clear color in
the sRGB color space. Limit the allowable clear colors for sRGB
fast-clears to 0/1 so that both color space requirements are satisfied.

Makes iris pass the sRGB -> sRGB subtest of the fcc-write-after-clear
piglit test on gen9+.

v2:
* Drop iris_context::blend_enables. (Ken)
* Drop some more resolve-related blend-state-tracking code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
2020-06-19 21:03:31 +00:00
Nanley Chery
48a3f4c44b iris: Avoid fast-clear with incompatible view
For rendering operations, avoid adding or using fast-cleared blocks if
the render format is incompatible with the clear color interpretation.
Note that the clear color is currently interpreted through the
resource's surface format.

Makes iris pass subtests of the fcc-write-after-clear piglit test:

* UNORM -> SNORM, partial block on gen8+.
* linear -> sRGB, partial block on gen9+.
* UNORM -> SNORM, full block on gen12.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
2020-06-19 21:03:31 +00:00
Nanley Chery
fbbf79377b iris: Remove the CCS_D fallback
Remove the CCS_D fallback logic so that iris doesn't attempt to use a
non-existent surface state for some renders. Also, add an assertion to
catch the issue.

The fallback in iris_resource_render_aux_usage can lead to this problem
because it doesn't account for the fact that surface states created from
resources with the Y_TILED_CCS modifier may only have CCS_E or NONE as
aux usages (due to iris_resource_create_with_modifiers).

Without this change, the next commit would have triggered the fallback
and regressed the following tests on gen9:

* dEQP-EGL.functional.wide_color.window_888_colorspace_srgb
* dEQP-EGL.functional.wide_color.window_8888_colorspace_srgb
* dEQP-EGL.functional.wide_color.pbuffer_888_colorspace_srgb
* dEQP-EGL.functional.wide_color.pbuffer_8888_colorspace_srgb

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
2020-06-19 21:03:31 +00:00
Nanley Chery
e533232d8c iris: Drop can_fast_clear_color's format parameter
Pull the resource's format from the pipe_resource instead. Makes the
changes in later commits more obvious.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
2020-06-19 21:03:31 +00:00
Eric Engestrom
7b7d28ed6d docs: move "stable" tag explanation next to Fixes:
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
2020-06-19 19:51:53 +00:00
Eric Engestrom
a096d41094 docs: move Fixes: tag explanation to its own section
This also adds the ability to link directly to it:
https://mesa3d.org/submittingpatches.html#fixes

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
2020-06-19 19:51:53 +00:00
Eric Engestrom
7488d49107 docs: make it clear that the tags needs to be in the commit message
Some people have been putting them only in the MR description, which
isn't picked up by our tools. (Note that doing both doesn't hurt.)

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
2020-06-19 19:51:53 +00:00
Eric Engestrom
731465192a docs: reword a sentence a bit
The "that you know ahead of time" bit just sounded weird as everything on this
page except the backport MR only applies if you know it "ahead of time".

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
2020-06-19 19:51:53 +00:00
Eric Engestrom
5d27d5eb61 docs: add some formatting to the "backport merge request" option
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
2020-06-19 19:51:53 +00:00
Eric Engestrom
0e4eb7b86d docs: prefer Fixes: over Cc: mesa-stable
`Fixes:` targets a specific commit and as such is much more precise and
useful than `Cc: mesa-stable`, so let's prefer it when applicable.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
2020-06-19 19:51:53 +00:00
Eric Engestrom
8fd9893123 docs: drop git sendemail instructions
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
2020-06-19 19:51:53 +00:00
Eric Engestrom
a29a1588b1 docs: reword "sending a patch revision" to "updating a merge request"
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
2020-06-19 19:51:53 +00:00
Eric Engestrom
fdebba2770 docs: stop considering Cc: mesa-stable as an email address
Our tools haven't needed more than this ^ for a while, and the historical
reasons this used to be an email address don't matter anymore.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5378>
2020-06-19 19:51:53 +00:00
Kristian H. Kristensen
b1a98a1107 freedreno/a6xx: Set index buffer size to bo size
The number of vertices may be out of bound and if we use it for
computing index buffer size we may get too big a size.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5552>
2020-06-19 19:25:34 +00:00
Kristian H. Kristensen
2580e4f921 freedreno/a6xx: Don't write REG_A6XX_RB_SRGB_CNTL in restore
We configure this as part of MRT set up.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5552>
2020-06-19 19:25:34 +00:00
Jason Ekstrand
77c50891b6 anv: Use resolve_device_entrypoint for dispatch init
There's no good reason to have the "which table do I use?" code
duplicated twice.  The only advantage to the way we were doing it before
was that we could move the switch statement outside the loop.  If this
is ever an actual device initialization perf problem that someone cares
about, we can optimize that when the time comes.  For now, the
duplicated cases are simply a platform-enabling pit-fall.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5530>
2020-06-19 19:13:56 +00:00
Eric Engestrom
e94a122642 docs: suggest alternative installation methods for meson
A couple of popular distros have a habit of never updating anything.
Point their users towards ways of using current versions of meson anyway.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2988>
2020-06-19 18:05:25 +00:00
Brian Ho
cca9aa4dfd turnip: Fill out VkPhysicalDeviceSubgroupProperties
This commit fills out VkPhysicalDeviceSubgroupProperties if present
in a VkPhysicalDeviceProperties2. The values here are simply pulled
from the blob.

Fixes some flakes in dEQP-VK.subgroups.* since dEQP was reading
uninitialized values of VkPhysicalDeviceSubgroupProperties.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5564>
2020-06-19 17:49:09 +00:00
Mike Blumenkrantz
292ade3c9d zink: use int assignment for vk int type
this breaks 32bit builds that use -Werror=int-conversion

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5545>
2020-06-19 17:31:51 +00:00
Rob Clark
8f11cc4cad freedreno/ir3: move output_loc to variant
This moves the last bit of important state to be serialized from
ir3_shader to ir3_shader_variant.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
640ff0e847 freedreno/ir3: move const_state back to variant
For shader-cache, we want to not have anything important in `ir3_shader`.
And to have shader variants with lower const size limits (to properly
handle cross-stage limits), we also want variants to be able to have
their own const_state.

But we still need binning pass shaders to align with their draw pass
counterpart so that the same const emit can be used for both passes.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
00926954c3 freedreno/ir3: un-embed const_state
Make it an rzalloc'd ptr instead of embedded struct, so it can serve as
the mem ctx for immediates.  This gets rid of needing to explicitly free
the immediates, so one less thing to deal with when moving const_state.
(Also, after we move const_state to the shader variant, we won't need
one for binning pass variants)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
ab74b792d4 freedreno/ir3: move num_reserved_user_consts out of const_state
When we move const_state to the variant, this will need to stay in the
shader, as it applies to all variants (and we need to store it somewhere
before we have any variants)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
74140c2e85 freedreno/ir3: convert over to ralloc
The `ir3_shader` is the root mem ctx, with `ir3_shader_variant` hanging
off that, and various variant specific allocations hanging off the
variant.

This lets us delete a bunch of cleanup code.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
6039d083f7 freedreno/ir3: pass variant to ir3_create()
Prep to convert over to ralloc.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Connor Abbott
65660622a1 ir3: Split out variant-specific lowering and optimizations
It seems a lot of the lowerings being run the second time were
unnecessary. In addition, when const_state is moved to the variant,
then it will become impossible to know ahead of time whether a variant
needs additional optimizing, which means that ir3_key_lowers_nir() needs
to go away. The new approach should have the same effect, since it skips
running lowerings that are unnecessary and then skips the opt loop if no
optimizations made progress, but it will work better when we move
ir3_nir_analyze_ubo_ranges() to be after variant creation.

The one maybe controversial thing I did is to make
nir_opt_algebraic_late() always happen during variant lowering. I wanted
to avoid code duplication, and it seems to me that we should push the
_late variants as far back as possible so that later opt_algebraic runs
don't miss out on optimization opportunities.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
f4654c458f freedreno/ir3: constify shader key
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
91ed8b7fe3 freedreno/ir3: drop shader->num_ubos
The only difference between this and `const_state->num_ubos` was that
the latter is counting # of ubos loaded via `ldg` (based on UBO addrs
in push-consts).  But turns out there isn't really any reason to care.
Instead just add an early return in the one code-path that cares about
the number of `ldg` UBOs.

This gets rid of one more thing we need to move from `ir3_shader` to
`ir3_shader_variant`.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
70fbd48b3a freedreno/ir3: move ubo_state into const_state
As with const_state, this will also need to move into the variant.  To
simplify that, just move it into the const_state itself, since after all
it is related.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
a8b995c055 freedreno/a6xx: defer userconst cmdstream size calculation
The `ubo_state` will also need to move to `ir3_shader_variant`.  But we
can prepare for that and simplify things a bit if we calculate the
cmdstream on first emit, once we already have the appropriate variant.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
bd55533f5b freedreno/ir3: add accessor for const_state
We are going to want to move this back to the variant, and come up with
a different strategy for binning/nonbinning to share the same constant
layout, in order to implement shader-cache support.  (Since then we
can have a mix of dynamically compiled variants and cache hits, so there
is no good place to serialize the const-state.)

To reduce the churn as we re-arrange things, move direct access to the
const-state to a helper fxn.  This patch is the boring churny part.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
1e8808a4a0 freedreno/ir3: refactor out helper to compile shader from asm
Deduplicate a bit of hand-building of ir3_shader/_variant from
computerator and delay test.  This also removes the need for
external things to depend on generated ir3_parser header.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Pierre-Eric Pelloux-Prayer
b6db703e0f st/mesa: make texture views inherit compressed_data storage
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2775
Fixes: c3fafa127a ("st/mesa: generalize code for the compressed texture map/unmap fallback")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5492>
2020-06-19 10:39:08 +02:00
Pierre-Eric Pelloux-Prayer
993c64e6fe ac/llvm: load 1 byte at a time if unaligned on gfx10
If buffer or stride is unaligned we use the same trick as on gfx6:
load 1 byte at a time and recompose the output if needed.
This change fixes lots of deqp/glcts tests:
  - dEQP-GLES2.functional.draw.random.1, 10, ...
  - dEQP-GLES2.functional.vertex_arrays.multiple_attributes.stride.3_float2_0_float2_0_float2_17, ...
  - dEQP-GLES2.functional.vertex_arrays.single_attribute.first.byte_first24_offset1_stride2_quads256, ...
  - dEQP-GLES2.functional.vertex_arrays.single_attribute.strides.buffer_0_17_byte2_vec4_dynamic_draw_quads_1, ...
  - dEQP-GLES31.functional.draw_indirect.random.14, ...

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5502>
2020-06-19 09:20:16 +02:00
Gert Wollny
bddfbfcb56 r600/sfn: Handle memory_barrier
I'm not sure whether this should actually be a barrier accross all
shader processing units, the TGSI code path seems to handle this
only by using GROUP_BARRIER, so let's do the same here.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
2020-06-19 06:58:07 +00:00
Gert Wollny
34e15cd610 r600/sfn: Take SSBO buffer ID offset into account
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
2020-06-19 06:58:07 +00:00
Gert Wollny
5aef9ea2a3 r600/sfn: Add support for reading cube image array dim.
The cube array size can't be queried directly, the number of array
elements must be passed via a constant buffer.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
2020-06-19 06:58:07 +00:00
Gert Wollny
e458683a52 r600/sfn: Add support for image_size
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
2020-06-19 06:58:07 +00:00
Gert Wollny
249dbcb769 r600/sfn: Add imageio support
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
2020-06-19 06:58:07 +00:00
Gert Wollny
b303540c48 r600/sfn: lower image derefs
v2: Signal lowering image derefs by using the CAP

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
2020-06-19 06:58:07 +00:00
Samuel Pitoiset
2ac5cce1a1 radv: require LLVM 11+ for GFX 10.3 if not using ACO
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5389>
2020-06-19 08:18:43 +02:00
Samuel Pitoiset
dc698fb5dc radv: add support for Sienna Cichlid
Bits copied from RadeonSI. Totally untested.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5389>
2020-06-19 08:18:41 +02:00
Samuel Pitoiset
8c144482ea aco: replace == GFX10 with >= GFX10 where it's needed
Assume the GFX10.3 ISA is similar to GFX10 which is likely (except
possible minor changes and new instructions for raytracing).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5389>
2020-06-19 08:18:39 +02:00
Samuel Pitoiset
3c28438094 radv: replace == GFX10 with >= GFX10 where it's needed
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5389>
2020-06-19 08:18:37 +02:00
Matt Turner
1f87106276 intel/tools: Add assembler tests for the cr0 register
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
2020-06-19 02:10:40 +00:00
Matt Turner
e573f21edd intel/tools: Disallow control subregisters > 3
> 4 was probably a typo, since the documentation says that there are 4
subregisters (0-3).

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
2020-06-19 02:10:40 +00:00
Matt Turner
cc6fc963f0 intel/tools: Require explicit regions/types for special regs
The docs say that these registers should  only be read with a certain
type, and I'm inclined to believe that the hardware behaves that way,
but it makes the assembler a little more confusing and also confuses the
user of the assembler that some operands don't take types or regions.

Just always requiring regions and types seems like the sensible thing.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
2020-06-19 02:10:40 +00:00
Matt Turner
9feb6302f9 intel/tools: Drop srctype from ipreg
It's unused, and it would cause shift/reduce conflicts after the next
patch.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
2020-06-19 02:10:40 +00:00