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Author SHA1 Message Date
Karmjit Mahil
1a250eeae3 pvr: Fix calculation in rogue_max_compute_shared_registers(). 
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18224>
 2022-08-25 06:51:53 +00:00
Karmjit Mahil
241f42d443 pvr: Compete pvr_calc_fscommon_size_and_tiles_in_flight(). 
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18224>
 2022-08-25 06:51:53 +00:00
Qiang Yu
4fc9125ca2 winsys/amdgpu: fix non-page-aligned sparse buffer creation 
ARB_sparse_buffer does not require sparse buffer size to be
page aligned. So we need to align it before VM ops as KMD
will check whether it's aligned and return EINVAL if not.

Fixes: 667da4eaed ("winsys/amdgpu: sparse buffer creation / destruction / commitment")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7104
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18206>
 2022-08-25 01:14:08 +00:00
Eric Engestrom
e767f54f28 v3d: introduce V3D_DBG() macro to make V3D_DEBUG checks consistent 
The main issue was the inconsistent use of `unlikely()`, but the macro
also simplifies the code a little bit.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18086>
 2022-08-24 23:03:57 +00:00
Eric Engestrom
e178ecf8a9 vc4: introduce VC4_DBG() macro to make VC4_DEBUG checks consistent 
The main issue was the inconsistent use of `unlikely()`, but the macro
also simplifies the code a little bit.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18086>
 2022-08-24 23:03:57 +00:00
Chad Versace
a771efdefe venus: Enable VK_EXT_pipeline_creation_cache_control 
The extension disrupts assumptions in venus. It gives
vkCreateFooPipelines an additional success code,
VK_PIPELINE_COMPILE_REQUIRED, which allows some pipelines to succeed
creation and others fail.

Tested with 'dEQP-VK.*cache_control*' at vulkan-cts-1.3.3.1.
  pass/fail/skip/warn = 15/0/0/3
Warnings were from long pipeline compiles on a full debug build in host
and guest.

See: https://gitlab.freedesktop.org/virgl/virglrenderer/-/merge_requests/890
Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17847>
 2022-08-24 22:50:33 +00:00
Chad Versace
f81915585d venus: Fix failure path on pipeline creation 
It's not sufficient to vk_free() the pipeline. We must also
vn_object_base_fini().

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17847>
 2022-08-24 22:50:33 +00:00
Chad Versace
ad8c8e366a venus: Dedupe pipeline handle creation 
Refactor the code into new function vn_create_pipeline_handles().

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17847>
 2022-08-24 22:50:33 +00:00
Eric Engestrom
c66622de3a meson: replace manual compiler flags with meson arguments 
These would only have worked in GCC and Clang, which so far wasn't an
issue, but let's clean it up anyway.

Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18190>
 2022-08-24 22:13:19 +00:00
Dave Airlie
76bcf69e33 vulkan: update rest of the headers to v1.3.225 
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18237>
 2022-08-24 20:12:43 +00:00
Alyssa Rosenzweig
5777f99fc5 pan/mdg: Use correct idiv lowering 
Rip off the bandaid. We can't tolerate straight-up wrong results. We have an
efficient umul_high implementation so it's not so bad.

total instructions in shared programs: 1537404 -> 1537204 (-0.01%)
instructions in affected programs: 143299 -> 143099 (-0.14%)
helped: 89
HURT: 283
helped stats (abs) min: 1.0 max: 41.0 x̄: 5.87 x̃: 6
helped stats (rel) min: 0.39% max: 6.67% x̄: 1.41% x̃: 1.44%
HURT stats (abs)   min: 1.0 max: 7.0 x̄: 1.14 x̃: 1
HURT stats (rel)   min: 0.24% max: 5.71% x̄: 0.35% x̃: 0.27%
95% mean confidence interval for instructions value: -0.96 -0.12
95% mean confidence interval for instructions %-change: -0.17% 0.03%
Inconclusive result (%-change mean confidence interval includes 0).

total bundles in shared programs: 647521 -> 648154 (0.10%)
bundles in affected programs: 45833 -> 46466 (1.38%)
helped: 92
HURT: 228
helped stats (abs) min: 1.0 max: 13.0 x̄: 3.10 x̃: 3
helped stats (rel) min: 0.69% max: 7.14% x̄: 2.11% x̃: 1.99%
HURT stats (abs)   min: 1.0 max: 7.0 x̄: 4.03 x̃: 5
HURT stats (rel)   min: 0.59% max: 7.22% x̄: 2.93% x̃: 3.40%
95% mean confidence interval for bundles value: 1.58 2.38
95% mean confidence interval for bundles %-change: 1.21% 1.76%
Bundles are HURT.

total quadwords in shared programs: 1135141 -> 1138268 (0.28%)
quadwords in affected programs: 101064 -> 104191 (3.09%)
helped: 30
HURT: 342
helped stats (abs) min: 1.0 max: 30.0 x̄: 4.97 x̃: 3
helped stats (rel) min: 0.24% max: 5.99% x̄: 1.72% x̃: 1.06%
HURT stats (abs)   min: 1.0 max: 16.0 x̄: 9.58 x̃: 10
HURT stats (rel)   min: 0.73% max: 17.14% x̄: 3.64% x̃: 3.80%
95% mean confidence interval for quadwords value: 7.84 8.97
95% mean confidence interval for quadwords %-change: 2.99% 3.43%
Quadwords are HURT.

total registers in shared programs: 91938 -> 92265 (0.36%)
registers in affected programs: 2639 -> 2966 (12.39%)
helped: 0
HURT: 280
HURT stats (abs)   min: 1.0 max: 3.0 x̄: 1.17 x̃: 1
HURT stats (rel)   min: 9.09% max: 50.00% x̄: 12.75% x̃: 11.11%
95% mean confidence interval for registers value: 1.12 1.22
95% mean confidence interval for registers %-change: 12.05% 13.45%
Registers are HURT.

total threads in shared programs: 55280 -> 55268 (-0.02%)
threads in affected programs: 24 -> 12 (-50.00%)
helped: 0
HURT: 11
HURT stats (abs)   min: 1.0 max: 2.0 x̄: 1.09 x̃: 1
HURT stats (rel)   min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -1.29 -0.89
95% mean confidence interval for threads %-change: -50.00% -50.00%
Threads are HURT.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17860>
 2022-08-24 19:54:23 +00:00
Alyssa Rosenzweig
5bc830cbf2 pan/mdg: Reexpress umul_high packing 
There are a bunch of subtle details of how 32-bit sources are
zero-extended to 64-bit, how their swizzles work, how 64-bit
destinations are shrunk to 32-bit, and how those two interact. This
fixes the interactions... mostly.

Fixes umul_high, all such tests should be passing now. Unblocks idiv
lowering that depends on umul_high.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17860>
 2022-08-24 19:54:23 +00:00
Alyssa Rosenzweig
7b78e05ba8 pan/mdg: Replicate swizzles for scalar sources 
This works around issue packing 32-bit scalar swizzles zero-extended to
64-bit, seen with the umul_high implementation. I tried for a while
figuring out the root cause (even rewrote a big chunk of disassembler)
but am still a bit lost. Nevertheless this is a safe workaround with no
performance impact (and avoids relying on NIR undefined behaviour to
implement GPU undefined behaviour), so let's do this for now to fix
umul_high.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17860>
 2022-08-24 19:54:23 +00:00
Marek Olšák
e951d6362c ci: update pass/fail results for spec@!opengl 1.0@gl-1.0-dlist-bitmap 
This is mostly positive.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17780>
 2022-08-24 18:13:02 +00:00
Marek Olšák
cbad4adc13 st/mesa: fix potential use-after-free in draw_bitmap_quad 
This is super unlikely to be freed before use, but let's fix it anyway.

setup_render_state calls set_sampler_views(take_ownership=true), which
means it takes ownership of the sampler view reference and is free to
unreference it, so we can't use sv after setup_render_state.

Fixes: feda6e9c5d - st/mesa: set take_ownership = true in set_sampler_views

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17780>
 2022-08-24 18:13:02 +00:00
Marek Olšák
bb860f63f6 mesa: create glBitmap textures while creating display lists 
This makes glCallList just a textured draw, which is blazingly fast.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17780>
 2022-08-24 18:13:02 +00:00
Marek Olšák
6da2fb81a7 Revert "mesa: implement a display list / glBitmap texture atlas" 
This reverts commit b26ddda12f and
commit 06d3b0a006.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17780>
 2022-08-24 18:13:02 +00:00
Lionel Landwerlin
f242c9af76 intel/fs: bump max SIMD size for A64 atomics with LSC 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>.
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
 2022-08-24 17:51:40 +00:00
Lionel Landwerlin
407f2beb97 intel/fs: port block a64/surface messages to use LSC 
v2: Fixup block load/store on surfaces/shared-memory (Rohan)

v3: drop write specific size_written case (Rohan)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
 2022-08-24 17:51:40 +00:00
Lionel Landwerlin
37b3601052 intel/fs: switch register allocation spilling to use LSC on Gfx12.5+ 
v2: drop the hardcoded inst->mlen=1 (Rohan)

v3: Move back to LOAD/STORE messages (limited to SIMD16 for LSC)

v4: Also use 4 GRFs transpose loads for fills (Curro)

v5: Reduce amount of needed register to build per lane offsets (Curro)
    Drop some now useless SIMD32 code
    Unify unspill code

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
 2022-08-24 17:51:40 +00:00
Lionel Landwerlin
3c6fa2703d intel/fs: fixup SEND validation check on overlapping src0/src1 
With the following SEND instruction :

   send(1)         nullUD          nullUD          g0UD            0x4200c504                a0.1<0>UD

This instruction although valid but somewhat nonsensical (SEND message
to write at offset contained in NULL register), triggers an error in
the validator.

The restriction is that we cannot have overlapping sources. The
validator not checking the type of register incorrectly thinks that
the null register (offset 0) is the same as g0.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
 2022-08-24 17:51:40 +00:00
Lionel Landwerlin
a81ca32f96 intel/fs: remove unused opcode 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
 2022-08-24 17:51:40 +00:00
Lionel Landwerlin
aa65f83203 intel/fs: switch compute push constant loads to LSC 
We're now able to load up to 8 GRFs in one send.

v2: Switch to use transpose + vector of up to 64 (Thanks Curro!)

v3: Increase parallelism by not reusing the same register for push
    constant offset (Curro)

v4: Drop dead ADD() instruction (Curro)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
 2022-08-24 17:51:40 +00:00
Mike Blumenkrantz
1e7a131fd1 tu: fix invalid free on alloc failure 
this is not an allocated pointer

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18230>
 2022-08-24 17:29:53 +00:00
Georg Lehmann
b3cc213f56 radv: Fold 16bit image sources. 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18106>
 2022-08-24 17:04:03 +00:00
Georg Lehmann
9151048957 aco: Combine 16bit undef and constants instead of using s_pack. 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18106>
 2022-08-24 17:04:03 +00:00
Georg Lehmann
46f6e2ddbb aco: Implement storage image A16. 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18106>
 2022-08-24 17:04:03 +00:00
Georg Lehmann
c8ad1aeeb2 nir/fold_16bit_tex_image: Add an option to fold image sources. 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18106>
 2022-08-24 17:04:03 +00:00
Gert Wollny
13355232e4 nir_lower_atomics_to_ssbo: Initialize deref struct 
This fixes the use of an uninitialzed value:

Conditional jump or move depends on uninitialised value(s)
  bcmp (vg_replace_strmem.c:1203)
  _mesa_add_sized_state_reference (prog_parameter.c:434)
  st_nir_assign_uniform_locations(gl_context*, gl_program*, nir_shader*) (st_glsl_to_nir.cpp:209)
  st_finalize_nir (st_glsl_to_nir.cpp:1041)
  by 0x58271B9: st_glsl_to_nir_post_opts(st_context*, gl_program*, gl_shader_program*) (st_glsl_to_nir.cpp:571)
  ...
Uninitialised value was created by a heap allocation
  malloc (vg_replace_malloc.c:381)
  ralloc_size (ralloc.c:114)
  ralloc_array_size (ralloc.c:218)
  deref_offset_var (nir_lower_atomics_to_ssbo.c:47)
  lower_instr (nir_lower_atomics_to_ssbo.c:111)
  nir_lower_atomics_to_ssbo (nir_lower_atomics_to_ssbo.c:204)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18227>
 2022-08-24 16:02:03 +00:00
Georg Lehmann
8eac45b274 nir: Add nir_ssa_scalar_is_undef. 
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18183>
 2022-08-24 15:22:40 +00:00
David Heidelberg
cfaff1d341 ci: fix leftover tag in image-tags.yml 
Fixes: eb6ce47d4f ("ci: Use mold for x86-64 and AArch64 builds")

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18228>
 2022-08-24 13:28:22 +00:00
Konstantin Seurer
78564b5b84 radv: Advertise subgroup ops for rt stages 
Closes: #7098
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18169>
 2022-08-24 13:05:38 +00:00
Mike Blumenkrantz
c4f78396d4 zink: support PIPE_CAP_FBFETCH_COHERENT 
that's what VK_EXT_rasterization_order_attachment_access is for

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18133>
 2022-08-24 12:19:13 +00:00
Mike Blumenkrantz
9f7195949b vulkan: Update the XML and headers to 1.3.225 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18133>
 2022-08-24 12:19:13 +00:00
Samuel Pitoiset
15a7361ce9 radv: merge gather_tess_info() with radv_fill_shader_info() 
Shouldn't introduce any functional changes. The dependencies between
stages might be improved with a new helper that will link shader_info.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18184>
 2022-08-24 11:17:05 +00:00
Samuel Pitoiset
7b94ca287b radv: remove unused num_tess_patches assignment for VS 
This is never used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18184>
 2022-08-24 11:17:05 +00:00
Samuel Pitoiset
068891a383 radv: remove unused tcs_vertices_out assignment for VS 
This is never used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18184>
 2022-08-24 11:17:05 +00:00
Samuel Pitoiset
76f33cbf25 radv: remove redundant assignment of tcs.tcs_vertices_out 
It's already assigned from radv_nir_shader_info_pass() and it's only
used to configure the VGT_TF_PARAM register. Otherwise, we read it
from NIR shader info during compilation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18184>
 2022-08-24 11:17:05 +00:00
Lucas Stach
762eefdbf6 etnaviv: mark instanced draw extensions as supported in docs/features.txt 
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18046>
 2022-08-24 09:13:31 +00:00
Lucas Stach
8b8beae8d5 etnaviv: expose ARB_draw_instanced 
Just set the pipe cap correctly. The InstanceID support is already
hooked up in the NIR compiler. All enabled piglit tests pass.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18046>
 2022-08-24 09:13:31 +00:00
Vinson Lee
1dffad2f83 zink: Remove duplicate variable zero. 
Fix defect reported by Coverity Scan.

Evaluation order violation (EVALUATION_ORDER)
write_write_typo: In zero = zero = nir_imm_zero(b, nir_dest_num_components(intr->dest), nir_dest_bit_size(intr->dest)),
zero is written twice with the same value.

Fixes: 0f97e317e3 ("zink: rewrite all undefined shader reads as 0001 instead of undef")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18164>
 2022-08-24 04:48:10 +00:00
Timothy Arceri
0c8492cd3b glsl: fix location for array subscript 
xfb_decl_assign_location() assumes that arrays are going to be packed.
But some conditions might prevent packing (e.g: explicit location or
smooth interpolation mode).

Instead of assuming that packing will happen, this commit adds a check to
determine if it'll happen and use the result to compute the proper location.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2214

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18175>
 2022-08-24 02:19:34 +00:00
Timothy Arceri
04e7ed8323 glsl: make packed varying helper needs_lowering() external 
We will use this helper to correctly calculate xfb offsets in the
following patch.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18175>
 2022-08-24 02:19:34 +00:00
Qiang Yu
ff7c59672f radeonsi: fix tcs_out_lds_offsets arg alignment 
tcs_out_lds_offsets is not sure to be 16 byte aligned, it's
calculated like this:

  num_patches * patch_vertices * lshs_vertex_stride

num_patches and patch_vertices are not sure to be any value aligned,
lshs_vertex_stride is added one extra dword, so it's only 4 byte
aligned.

This may cause problem even before we switch to nir tess output
lower when write tess factor before read tail of input. But it's
more likely to cause problem after we switch to nir tess output
lower because the main body won't eliminate the low 4bit offset
but epilog will, so they use different offset to read/write tess
factor.

Fixes: 7598bfd768 ("radeonsi: replace llvm tcs output with nir lower pass")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7083
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18174>
 2022-08-24 02:04:15 +00:00
Caio Oliveira
bee2df64d2 intel/compiler: Use fs_reg helpers for GS icp_handle selection 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18221>
 2022-08-24 01:42:23 +00:00
Caio Oliveira
b4aff6ab49 intel/compiler: Use fs_reg helpers for TCS icp_handle selection 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18221>
 2022-08-24 01:42:22 +00:00
Caio Oliveira
a1b1fdf70d intel/compiler: Rename 8_PATCH to MULTI_PATCH 
Make it clearer we are dealing with multiple patches,
works better in constrast with SINGLE_PATCH.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18151>
 2022-08-24 00:39:57 +00:00
Caio Oliveira
7cd06249b9 intel/compiler: Remove INTEL_DEBUG=tcs8 
For Gen11 and prior, the dispatch mode for TCS was SINGLE_PATCH, and
this debug setting could be used to change it to 8_PATCH (falling back
to SINGLE_PATCH when shader couldn't be in the multi dispatch mode).
However after talking to Ken, seems this debug setting is not really
worth keeping around, so removing it.

For Gen12+ the only option is 8_PATCH, so it was always using that
dispatch mode as before.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18151>
 2022-08-24 00:39:57 +00:00
Bas Nieuwenhuizen
bb2a444324 vulkan/wsi: Take max extent into consideration for modifier selection. 
For AMD we kinda have some modifiers with a max size ... (Which is
really a compositor/kms issue, but getting them to try kinda falls
into the unsolved  "how to allocate/what pitch to use" bucket, so
we solve it on the allocating side)

Cc: mesa-stable
Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18139>
 2022-08-23 23:36:53 +00:00
Daniel Stone
eb6ce47d4f ci: Use mold for x86-64 and AArch64 builds 
mold is a fancy new linker that's really fast.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6877
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17992>
 2022-08-23 23:12:07 +00:00