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Author SHA1 Message Date
Rob Clark
d7f141bb35 freedreno/ir3: Add cat5/cat6 nonuniform flag 
Not yet used by the compiler, but needed so we don't loose information
between ir3 parser and instruction encoding.

Currently ignored for cat5, because the uniform vs non-uniform default
is swapped there.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
101bf686ee freedreno/ir3: Disambiguate a6xx+ "bindless" instructions 
Add a `.b`.. for the atomic instructions it should be `atomic.b.op` but
for now put the `.b` at the end to simplify life for the existing disasm

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
c55737902c freedreno/ir3: Don't leak disk_cache 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
71f902bab9 freedreno/ir3: Add parsing and assembler testing 
In theory we should be able to round-trip from disasm->asm and get a
bitwise match.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
b91319d952 freedreno/ir3: Tweak ldib/resinfo encoding 
The blob is using '0' for the low bit in these (except for ldib where it
seems to randomly use either '0' or '1').  The upcoming xml based ISA
spec maps this bit to 'dontcare' in the ldib case.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
99908c8d6d freedreno/ir3/parser: Add initial cat6 IBO instructions 
Well, really just resinfo.. dealing with the different ldib/stib syntax
for a6xx+ vs earlier seems a bit too painful to deal with.  But resinfo
at least gives us some encoding test coverage of this group of instrs.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
f9c76fba9d freedreno/ir3/parser: Relative gpr/const can have modifiers too 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
594b004e00 freedreno/ir3/parser: Add missing (sat) modifier 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
77552cbdda freedreno/ir3: Don't set bit for dest conversion for p0.c 
This appears to be ignored when writing to predicate registers (which I
guess makes sense, since they are boolean).  So no real harm in setting
it, other than it makes some of the ir3_parser test vectors not match
the expected result for encoding.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
1cdff35361 freedreno/ir3/parser: Fixup cat5 s2en instructions 
Currently ir3 (incl emit_cat5()) expects the samp/tex src register to be
first.. which requires some fixup for the parser to match.

TODO we might want to revisit the src reg order when adding new instr
packing/encoding.  For now, lets just make the parser match the rest of
ir3.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
d35c79614e freedreno/ir3/parser: Fix dsxpp/dsypp encoding 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
e9b3234915 freedreno/ir3/parser: Fix cat6 store encoding 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
b90a1cf747 freedreno/ir3: Cleanup cat6 load instructions 
There was some src2 vs src3 confusion, but since the syntax is like:

   ldl.f32 rDst, l[rBase+off], ncomp

it makes more sense to call the offset src2 and ncomp src3, than the
way we had it.  This is also easier to deal with for the ir3 assembly
parser.

Also, src_offset was only ever used by the assembly parser, and was
handled incorrectly in emit_cat6(), resulting that cat6 load instrs
would not work properly in (for ex) computerator.  Since we are
cleaning things up, drop src_offset and make the asm parser work in
the same way as the nir->ir3 frontend.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
4e272003b1 freedreno/ir3: Clean up instruction creation 
Convert everything remaining over to the version which takes # of
register (src + dst) and drop the ir3_instr_create2() version.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
d968f46997 freedreno/ir3/parser: Handle half-immed 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
68be24dd6c freedreno/ir3/parser: cat1 updates (mova1, movmsk) 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
647d7fc36d freedreno/ir3/parser: cat1 instructions can write relative GPR 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
0b36044d4f freedreno/ir3/parser: Add new cat0 instructions 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
2dc6458563 freedreno/ir3: Various cat0 updates 
Update the IR and packer to handle the additional cat0 fields, in
prep for adding support in the assembler (in prep for adding round
trip parsing/packing test coverage).

We don't actually use these yet from the ir3 compiler, but at least
this is one less thing to worry about when we start trying to use
them.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
eec183c159 freedreno/ir3/parser: Reset lexer when input changes 
Otherwise, in case of parse errors, the lexer state can still contain
buffered input from the previous parse.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
7b2d2bafe4 freedreno/ir3: Move assembler error handling 
Move out of ir3_parse_asm() so we can re-use it in disasm test for
round-tripping asm/disasm.  We don't want failures to be fatal (yet)
as there are still some things missing from the assembler.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
a928d0ab46 freedreno/ir3: Add some more disasm test vectors 
Various things that I noticed which were initially wrong with the xml
based disasm.

These were extracted from a collection of unique instructions extracted
from deqp traces, which unfortunately looses the link back to the
original test case.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
2933d54992 freedreno/ir3: Fix mova1 disasm 
Yet another mnemonic for mov

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Rob Clark
e3bd9aaf6b freedreno/ir3: Fix half-immed decoding issues 
For mov, half-float immeds are packed in 16b.  In other cases, the
syntax for a half-immed is a bit different (ie. `h(1)`)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Connor Abbott
6f35ebd8a5 ir3: Support MOVMSK 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Connor Abbott
5d36f36454 ir3: Better rules for shared src copy propagation 
It turns out that the actual rule for when a source/dest can be shared
is that it has to be cat1, cat2, or cat3. Allow this and silence
warnings.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Connor Abbott
f9804673fb ir3: Rename high registers to shared registers 
This more accurately reflects what they are.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
 2021-01-06 16:46:52 +00:00
Danylo Piliaiev
2b29ec7ca4 freedreno: Enable GLSL 3.30, updating us to GL 3.3 contexts 
All necessary features are already supported.

GL33 CTS failures:
 KHR-GL33.texture_swizzle.smoke - timeouts, passes otherwise
 KHR-GL33.cull_distance.coverage - see
  https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/2673
  fix is not in the public repo yet.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8270>
 2021-01-06 15:54:54 +00:00
Christian Gmeiner
4da67157db pan: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
c6d65bb01e microsoft/compiler: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
23c963f11b anv: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
c5a9270109 intel/compiler: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
fc3ce00791 intel/blorp: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
241fb75485 vc4: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
3d9c5d8a7d iris: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
9dd43c9232 d3d12: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
32bd47f6fa tu: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
d3a9770824 zink: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
fbfdc17b14 st: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
d46a761e9e ir3: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
172e79d009 v3dv: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
66d51965af v3d: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
c0fe111d64 nir: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
02553d96c8 tgsi_to_nir: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Christian Gmeiner
475f086056 mesa/prog_to_nir: use intrinsic builders 
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
 2021-01-06 14:34:41 +00:00
Mike Blumenkrantz
b5fb66a5ed nir: preserve explicit_binding in lower_atomics_to_ssbo 
it's important to be able to tell whether this is explicitly set by the
user

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7489>
 2021-01-06 12:56:09 +00:00
Erik Faye-Lund
8553e1cb71 zink: remove support for fcsel 
fcsel is only emitted by bool -> float lowering. We used to do that a
long time ago, but no longer. So we don't need to support this opcode
any longer.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8347>
 2021-01-06 12:49:48 +00:00
Erik Faye-Lund
cfb5ce782c zink: also lower scmp for soft-fp 
We recently added two versions of these options, due to soft-fp support.
So let's also add the lowering to the soft-fp version.

Fixes: 43302ead38 ("zink: use lower_scmp instead of open-coding")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8347>
 2021-01-06 12:49:48 +00:00
Boris Brezillon
471fd78e3c panfrost: Fix AFBC on Bifrost v6 
The AFBC layout of RT/ZS-extension descriptors on Bifrost v6 matches the
v7 one except for the Block Format field. Update the set_buf() functions
accordingly.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8328>
 2021-01-06 10:12:51 +01:00
Yogesh mohan marimuthu
8a22fc9502 radeonsi: enable vrs2x2 coarse shading if flat shading (v9) 
Enable vrs2x2 coarse shading if flat shading as per
idea and guidance given by Marek.

is_flat_shading variable in struct si_shader_info is set
based on the data from gather_intrinsic_info() function
and struct si_state_rasterizer. If is_flat_shading_variable
is set, then in function si_emit_db_render_state() vrs2x2
shading is enabled in hardware.

v2: Fix review comments from Pierre-Eric. Code optimizations.
v3: Fix indentation style issue.
v4: Fix review comments from Marek. Fixed logical issue pointed
    by Marek where info->is_flat_shading variable can be corrupted
    and other code cleanup.
v5: Make the code compact as suggested by Pierre-Eric.
v6: Fix new review comments from Marek.
v7: use info->uses_interp_color variable fix from Marek.
v8: Fix coding style comment from Marek.
v9: Add uses_fbfetch_output check as suggested by Marek.

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8161>
 2021-01-06 10:12:10 +05:30