Commit Graph

184451 Commits

Author SHA1 Message Date
Danylo Piliaiev
cdadead230 tu/a7xx: Make A7XX_RB_UNKNOWN_8E06 value configurable per-gen
It is some kind of DBG register which has different value
on different gens.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:12 +00:00
Sagar Ghuge
98b62434bd intel/compiler: Lower texture operation to combine LOD and AI
We have to push the lowering of texture operations a bit further in
pipeline since nir_lower_tex gets invoked twice and if there is no LOD
source present, nir_lower_tex adds that as a source. Once that's all
done we can easily combine the LOD and array index into a single 32-bit
value.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27458>
2024-02-12 21:25:48 +00:00
Sagar Ghuge
c984d6e2fc nir: Drop intel specific lowering code
In previous patches, we have moved the Intel specific lowering code in
brw_nir_lower_texture file. We can go ahead and drop the Intel specific
texture source too.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27458>
2024-02-12 21:25:48 +00:00
Sagar Ghuge
15129c7634 intel/compiler: Use nir_tex_src_backend1 to pack LOD and array index
Since this lowering is totally Intel specific, we don't have to
introduce the new texture source. We can use the nir_tex_src_backend1
source to pack LOD/LOD Bias and array index into 32 bit single value.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27458>
2024-02-12 21:25:48 +00:00
Sagar Ghuge
73a3257968 intel/compiler: Add texture operation lowering pass
This pass combines the LOD or LOD bias and array index into a single
32-bit value since Xe2+ sampler messages requires us to do that.

v2: (Alyssa)
- Use nir_iand_imm instead of nir_iand and nir_imm_int
- Use nir_trim_vector instead of nir_swizzle

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27458>
2024-02-12 21:25:48 +00:00
Lionel Landwerlin
646a7c864d anv: re-introduce BO CCS allocations
On Gfx12.0, CCS allocations have to be allocated per image because the
format of the image goes into the AUX-TT PTEs. The effect on memory
allocations is limited since the main surface granularity in the
AUX-TT PTE is 64KB.

On Gfx12.5, the granularity of the AUX-TT PTE is 1MB. This creates a
lot of waste in the application memory allocations. Fortunately the HW
doesn't care about the format put into the PTEs anymore. So it becomes
possible to have 2 images share the same PTE.

To implement this we bring back an earlier version of AUX-TT mappings
where we used to allocate additional CCS space at the end of the
VkDeviceMemory objects. On Gfx12.5, if the BO has additional CCS
space, we will now map the main surface to that space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin
bd197c6bcf intel/aux_map: add helper to compute offset in aux data
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin
c0889a127b intel/aux_map: add BSpec reference
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin
da6484a8a4 anv: use address helper to compute address u64 value
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin
7763e75eea anv: move ALLOC_HOST_CACHED_COHERENT as define
That way gdb can decode the other flags when looking at the variables.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin
3f64ec141e isl: add a no-aux-align usage flag
This flag signals that the driver will be dealing with aux-tt
alignment requirements on its own.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin
44515bb92c isl: printout sparse usage
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Rhys Perry
926d9f1cef radv: support minmax filter for more formats
Support should be the same as AMDVLK, except for these formats:
- VK_FORMAT_R4G4_UNORM_PACK8
- VK_FORMAT_A4R4G4B4_UNORM_PACK16_EXT
- VK_FORMAT_A4B4G4R4_UNORM_PACK16_EXT
- VK_FORMAT_A1B5G5R5_UNORM_PACK16_KHR
- VK_FORMAT_A8_UNORM_KHR
- VK_FORMAT_X8_D24_UNORM_PACK32
- VK_FORMAT_D24_UNORM_S8_UINT
And the various emulated compressed formats.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27551>
2024-02-12 20:05:27 +00:00
Faith Ekstrand
05cf04ac97 nvk: Convert shader addresses to offsets in nvk_shader.c
Fixes: e162c2e78e ("nvk: Use VM_BIND for contiguous heaps instead of copying")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27565>
2024-02-12 18:47:07 +00:00
Faith Ekstrand
afd42f5951 nvk/heap: Rework over-allocation
Instead of making it part of every BO, just reserve a bit of space at
the end of the top buffer as part of setting up our vma_heap.  This
reduces our memory allocation by nvk_heap::overalloc per BO and means
that the over-allocation is taken into account when sparse binding heap
BOs in the contiguous case.

Fixes: e162c2e78e ("nvk: Use VM_BIND for contiguous heaps instead of copying")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27565>
2024-02-12 18:47:07 +00:00
Faith Ekstrand
728256e994 nvk/heap: Use nvk_heap_bo::addr instead of bo->offset
Fixes: e162c2e78e ("nvk: Use VM_BIND for contiguous heaps instead of copying")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27565>
2024-02-12 18:47:07 +00:00
Faith Ekstrand
83521dd486 nvk: Don't set CONSTANT_BUFFER_SELECTOR with a zero size
Kepler complains about this and it's unnecessary since we set
ENABLE_FALSE whenever we have a zero size anyway.

Fixes: 55413e33dc ("nvk: Disable all cbufs in nvk_queue_init_context_draw_state()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27565>
2024-02-12 18:47:07 +00:00
Sviatoslav Peleshko
28ad2f488a anv: Store host-located copy of NULL surface state for faster memcpy
Real null_surface_state is located in the GPU memory, so copying from
there will be slow for dGPUs.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10594
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27577>
2024-02-12 17:48:15 +00:00
Neil Armstrong
48a0a3112f freedreno: Add a750 clock gating control related registers
The A750 doesn't have an HWCFG clock gating control but instead a set
of additionnal RBBM registers, add them to allow setting up hardware clock
gating on the A750 GPU.

Registers definitions are used from [0] and [1].

[0] https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/graphics-kernel/-/blob/gfx-kernel.lnx.14.0.r3-rel/gen7_reg.h#L636
[1] https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/graphics-kernel/-/blob/gfx-kernel.lnx.14.0.r3-rel/adreno_gen7.c#L490

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27576>
2024-02-12 17:10:09 +00:00
Konstantin Seurer
097e543c0a Revert "zink: always force flushes when originating from api frontend"
This reverts commit 03f049f497.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27560>
2024-02-12 16:47:30 +00:00
Konstantin Seurer
aed5e4e1f2 zink: Always set mfence->submit_count to the fence submit_count
Fixes glFinish not finishing all GPU work.

cc: mesa-stable

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8257
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27560>
2024-02-12 16:47:30 +00:00
David Rosca
8d44a11508 radeonsi/vcn: Don't reinitialize encode session on bitrate/fps change
When bitrate or fps change is detected, only update rate control
parameters instead of completely reinitializing encode session.

This fixes an issue where if application changed bitrate or fps often,
the output bitrate would significantly overshoot the target bitrate in some
cases. In other cases, the output bitrate would be extremely low instead.

Cc: mesa-stable

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27548>
2024-02-12 16:00:39 +00:00
Lionel Landwerlin
e0b4dfbbda anv: don't unmap AUX ranges at BO delete
It is possible to free memory backing images before images are
destroyed :

   VkFreeMemory:

   "Memory can be freed whilst still bound to resources, but those
    resources must not be used afterwards."

The spec leaves us the option to keep a reference on the associated
memory and free it only when all the bound resources have been
destroyed. Here we choose to free memory immediately.

One particular test in the CTS
(dEQP-VK.synchronization.internally_synchronized_objects.pipeline_cache_graphics)
does the following :

   imgA = vkCreateImage()
   imgB = vkCreateImage()
   memA = vkAllocateMemory()
   vkBindImageMemory(imgA, memA) # Aux mapping with ref count = 1
   vkFreeMemory(memA)            # Aux mapping removed, ref count = 0
   memB = vkAllocateMemory()     # Same address as memA
   vkBindImageMemory(imgB, memB)
   vkDestroyImage(imgA)	         # Removes the mapping of imgB-memB

   vkQueueSubmit()               # hang with pagefault in AUX-TT

The solution implemented in this change is to not do anything AUX-TT
related in vkFreeMemory(). This soluation has some consequences,
because a virtual memory address range freed and reallocated cannot be
rebound in the AUX-TT until all the associated resources have released
their AUX-TT mapping (to bring back the AUX-TT refcount of the range
to 0). This should still be better than keeping the memory allocated
through refcounting of the anv_bo.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7b87e1afbc ("anv: track & unbind image aux-tt binding")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10528
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27566>
2024-02-12 15:37:18 +00:00
Konstantin Seurer
fb62bffcda radv: Wire up ac_gather_context_rolls
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27322>
2024-02-12 14:04:24 +00:00
Konstantin Seurer
ba6d6e5ee1 amd/common: Use the correct register table for GFX10_3
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27322>
2024-02-12 14:04:24 +00:00
Timothy Arceri
1098afd7fb gallium: add PIPE_CAP_FP16 for AMD_gpu_shader_half_float
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri
6fbf336788 compiler/types: Add a contains_32bit helper
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri
5f1f6d7496 glsl: add half float AMD_shader_trinary_minmax functions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri
d619c16c3f glsl: add half float derivative functions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri
14de2eff89 glsl: add half float interpolation functions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri
9dc5eec02c glsl: allow half float varyings
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri
3dc67c2c7e glsl: add half float vector relational functions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri
e7f1be1ceb glsl: add half float matrix functions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri
99a80ac930 glsl: add half float geometric functions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri
6a170051a9 glsl: add support for half float packing functions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri
c386d56915 glsl: add half float support for common functions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri
eea1c1fa7b glsl: add f2f16() helper to ir_builder
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri
94865a45f8 glsl: add half float exponential functions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri
829c99def1 glsl: add half float angle and trigonometry functions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:13 +00:00
Timothy Arceri
3ff22ee4ae glsl: add some new helpers for half float builtin functions
These helpers will be used in the following patches.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:13 +00:00
Timothy Arceri
9dc651a13f glsl: skip conversion of half float back to float for GL queries
This is only needed for GLES where floats have been lowered to
half floats internally. We don't do that in desktop GL and we
need to skip it to return the correct enums for the
AMD_gpu_shader_half_float extension.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:13 +00:00
Timothy Arceri
66633dbbd0 glsl: add ubo packing support for half floats
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:13 +00:00
Timothy Arceri
5803417c67 glsl: add implicit half float conversions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:13 +00:00
Timothy Arceri
b83477973f glsl: add glsl_type_is_float_16() helper
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:13 +00:00
Timothy Arceri
5eea4c42f5 glsl: update assert to allow for half float support
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:13 +00:00
Timothy Arceri
b2a7717717 glsl: add explicit half float conversion support
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:13 +00:00
Timothy Arceri
edbe1b5bb4 glsl: add half float support to the parser
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:13 +00:00
Timothy Arceri
72fb49516e glsl: add basic params for AMD_gpu_shader_half_float extension
This sets us the basic infrastructure to required to add an
extension.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:13 +00:00
Jani Nikula
d8e4a4e44b docs: fix doc build 'intel/dev/intel_device_info_gen.h' file not found
Commit a52c1994aa ("intel/dev: generate declarations for struct
intel_device_info") started generating and including
intel/dev/intel_device_info_gen.h, but it's not present in the
documentation build, leading to errors:

docs/isl/formats.rst:222: ERROR: src/intel/dev/intel_device_info.h:39: 'intel/dev/intel_device_info_gen.h' file not found
docs/isl/tiling.rst:87: ERROR: src/intel/dev/intel_device_info.h:39: 'intel/dev/intel_device_info_gen.h' file not found

Add an empty header stub under docs/header-stubs to fix the build.

Fixes: a52c1994aa ("intel/dev: generate declarations for struct intel_device_info")
Signed-off-by: Jani Nikula <jani@nikula.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27573>
2024-02-12 14:09:39 +02:00
Corentin Noël
b0af2b30ab ci_run_n_monitor: Allow the upstream format to not exist
When pushing directly to a fork, the upstream branch does not exist and thus
returns an empty string.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27567>
2024-02-12 10:52:53 +01:00