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Author SHA1 Message Date
Gert Wollny
ccff97f7ba tsan-blacklist: Ignore race in get_max_abs_timeout_ns 
The returned value is independent of the race, so surpress it.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28650>
 2024-04-11 13:52:36 +00:00
Gert Wollny
9e7112f4df llvmpipe: Don't emit certain debug code when TSAN is enabled 
It produces race conditions and is probably not interesting when running
TSAN.

v2: use #if and define values instead of "#if defined" (Yonggang Luo)
v3: remove some leftover text
v4: drop ws changes (Yonggang Luo)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28650>
 2024-04-11 13:52:36 +00:00
Gert Wollny
7c36c4f0a4 tsan-blacklist: ignore race when reading lp_fence signalled status 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28650>
 2024-04-11 13:52:36 +00:00
Gert Wollny
7dc19d941e util/u_queue: read fence->signalled locked with TSAN 
When TSAN is enabled we use standard mutexes instead of futexes. With
futexes the fence->signalled is read using an atomic operation, to best
mimic this let's protect the read with a locked mutex.

This avoids TSAN reporting a race condition (false positive with
futexes) with Zink when accessing the pipeline cache.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28650>
 2024-04-11 13:52:36 +00:00
Gert Wollny
aa347029da futex: disable futexes when compiling with tsan 
Thread sanitizer doesn't support futexes, so don't use them in this case
and fall back to standard mutexes. With that we can avoid tsan reporting
a large number of false positives.

v2: use #if instead of #ifdef to test the value of the define

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28650>
 2024-04-11 13:52:36 +00:00
Gert Wollny
0d46e0e88b meson: Add blacklist when compiling with tsan 
Check whether the compiler actually supports it and if
not than warn about it. Note that meson will also
suggest that one should use the build-in flag, but this
is just sloppy testing for -fsanitize, -fsanitize-blacklist
is actually not available as build-in option.

v2: define THREAD_SANITIZER to 1 or 0 (suggested by Yonggang Luo)
v3: Update comment about meson warning (Dylan Baker)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28650>
 2024-04-11 13:52:36 +00:00
Vignesh Raman
446672f9b1 ci: Implement support for replaying ANGLE restricted traces 
ANGLE traces must be compiled together with binaries into binary format.
Introduce them for AMD Raven device, replaying on Vulkan (radv).

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24270>
 2024-04-11 12:13:34 +00:00
Jonathan Gray
094a0a2ccb intel/dev: 0x7d45 is mtl-u not mtl-h 
Ref: https://ark.intel.com/content/www/us/en/ark/products/237327/intel-core-ultra-7-processor-155u-12m-cache-up-to-4-80-ghz.html
Ref: Core Ultra Processor Datasheet, Doc. No.: 792044, Rev.: 002
Fixes: 48ff68820e ("intel/dev: Enable MTL PCI ids")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27973>
 2024-04-11 10:03:40 +00:00
Jordan Justen
5238b773b4 intel/dev: Change ATS-M 0x56c2 string from 170G to 170V 
Ref: bspec 44477
Ref: 9123b5d5b0
Fixes: ce900dcbb1 ("intel/dev: Add ATS-M PCI ID for Data Center GPU Flex 170G")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28687>
 2024-04-11 07:38:21 +00:00
Georg Lehmann
5e6e3c7f89 nir: rename to nir_opt_16bit_tex_image 
Not sure what I was thinking when I wrote this pass (probably not much),
but opt makes more sense and matches other nir passes.
Fold is usually used for constants, and this pass handles more than those.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28662>
 2024-04-11 06:10:33 +00:00
Dave Airlie
16682b6054 radv/video: don't advertise timestamp bits for decode/encode 
At this point I'm not sure if the queues can support timestamps.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
 2024-04-11 13:40:04 +10:00
Dave Airlie
ee64a385b6 radv/video: handle encode control parameters better. 
The spec clarifies different operations for the reset flags,
just clean it up to follow it better.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
 2024-04-11 13:40:04 +10:00
Dave Airlie
05cd42417f radv/video: enable video encoding behind perftest flag 
This probes the vcn firmware version to make sure it can support
the encode extensions properly, then uses the perf test flag if so.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
 2024-04-11 13:40:02 +10:00
Dave Airlie
967e4e09de radv/video: add h265 encode support 
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
 2024-04-11 13:40:02 +10:00
Dave Airlie
54d499818c radv/video: add initial support for encoding with h264. 
This adds the encoding infrastructure along with support for h264.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
 2024-04-11 13:28:32 +10:00
Dave Airlie
800c03ffbd radv/video: add parameter patching calls. 
This is just infrastucture for encoding to plug into to patch
session parameters at create time.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
 2024-04-11 12:57:13 +10:00
Dave Airlie
1d74661dfd radv: add encoder queue support pieces and encoder queries. 
This is just checks for events and avoiding an assert in the winsys,
and adds support for the encoder queries.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
 2024-04-11 12:57:05 +10:00
Dave Airlie
f6c27bea26 radv: add direct cs emit for a dword. 
This lets you write a dword at a certain location, this is needed
for the encode queues.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
 2024-04-11 12:48:29 +10:00
Dave Airlie
1ce215c5a3 radv/video: export unified queue header/tail functions. 
These will be used for encode as well.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
 2024-04-11 12:48:26 +10:00
Dave Airlie
1e16851ab1 vulkan/video: copy the profile over for h264 encode. 
This allows is to use it for encoding h264 headers.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25900>
 2024-04-11 12:48:22 +10:00
Eric Engestrom
24b6a047ee docs: add sha256sum for 24.0.5 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28680>
 2024-04-11 01:32:09 +00:00
Eric Engestrom
ead2f6d7f1 docs: update calendar for 24.0.5 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28680>
 2024-04-11 01:32:09 +00:00
Eric Engestrom
030473f5b2 docs: add release notes for 24.0.5 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28680>
 2024-04-11 01:32:09 +00:00
Timur Kristóf
cfb8f3c1a5 radv: Clean up gathering linked I/O info. 
The code is more concise now without these helpers.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28488>
 2024-04-11 00:44:45 +00:00
Timur Kristóf
0e481a4adc radv: Always use fixed I/O locations for TCS outputs in VRAM. 
The goal of this patch is to make the TCS->TES shader I/O
independent of assigned I/O driver locations.

Always using the unlinked approach means a larger stride when
calculating some memory addresses, but otherwise should have no
perf impact whatsoever, because this only affects how TCS
outputs are stored to VRAM, and doesn't affect how they are
stored in LDS.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28488>
 2024-04-11 00:44:45 +00:00
Timur Kristóf
892ebf2040 radv: Add radv_gather_unlinked_io_mask to shader info header. 
We will call this from another file.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28488>
 2024-04-11 00:44:45 +00:00
Timur Kristóf
e8ddf1a064 radv: Remove dead code for creating per-patch IO mask. 
Not relevant or necessary anymore.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28488>
 2024-04-11 00:44:45 +00:00
Timur Kristóf
66f4dd292c radv: Keep track of TCS outputs that need LDS. 
Instead of reserving LDS space for all TCS outputs, we will now
only reserve it for TCS outputs which really need it, ie. those
which are read by the TCS.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28488>
 2024-04-11 00:44:45 +00:00
Georg Lehmann
b44f97a7ba nir: don't try to optimize exclusive min/max scan to inclusive 
SPIR-V rules for fmax/fmin scans are *very* stupid.
The required identity is Inf instead of NaN but if one input
is NaN, the other value has to be returned.
This means for invocation 0:
min(subgroupExclusiveMin(NaN), NaN) -> Inf
subgroupInclusiveMin(NaN) -> undefined (NaN for any sane backend)

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27536>
 2024-04-11 00:03:13 +00:00
Lucas Stach
df63f188e8 etnaviv: fix separate depth/stencil clears 
TS only tracks the clear state on a per-tile basis, so for a combined
depth/stencil buffer there is no way to fast-clear the one without also
affecting the other. Fall back to a regular clear when the clear_bits
tell us that not all channels of the buffer are to be cleared and make
sure to flush/invalidate any pending TS state when we do so.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28668>
 2024-04-10 23:46:01 +00:00
Erik Kurzinger
c1401fda8a wsi/wayland: don't use explicit sync with sw 
When using software rendering with the Wayland WSI we should not try to
use explicit sync even if it is supported by the compositor. Not only is
it not necessary in that case, but the protocol explicitly disallows
using it with shared memory buffers.

As a fix, first we modify wsi_configure_cpu_image to not set
info->explicit_sync to true for CPU images. However, we still want the
implicit_sync parameter in wsi_create_buffer_blit_context to be set to
false since CPU images don't need implicit sync either. To ensure that
remains so, we add a new field to wsi_image_info tracking the image
type, and then only enable implicit sync for DRM images when explicit
sync is not supported.

Additionally, we modify wsi_wl_use_explicit_sync to return false when
device->sw is true.

Signed-off-by: Erik Kurzinger <ekurzinger@nvidia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28678>
 2024-04-10 23:08:36 +00:00
David Heidelberg
44db558cea ci: disable sona devices, all devices are offline 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28683>
 2024-04-10 22:41:20 +00:00
Connor Abbott
c0867f4811 freedreno/afuc: Add initial support for a750 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28628>
 2024-04-10 21:51:59 +00:00
Connor Abbott
04af4cbfea freedreno/afuc: Add a7xx new-style branch instructions 
It turns out that what I guessed was "preemptleave" was actually "bl"
which writes a return address to $1b which I've renamed $lr. On a750
this is combined with a new indirect jump instruction to create a more
"standard" function call ABI in the AQE firmware using $lr and $1a which
is $sp. This ABI is used for what appears to be compiled functions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28628>
 2024-04-10 21:51:59 +00:00
Connor Abbott
9c0ba24c70 freedreno/afuc: Switch to using the GPU ID in the firmware 
Starting with a750, the control registers are shuffled around even
though the ISA is compatible. The format of the file name also changes.
This would make support convenient, except that there is already a
perfectly good way to ID the hardware that we aren't using: the first
dword contains a hardware version field in addition to the firmware
version. Use this field as the ID that determines everything else (ISA
version, control register layout to use, etc.). This means that when
assembling and disassembling we must parse the first dword in order to
get it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28628>
 2024-04-10 21:51:59 +00:00
Samuel Pitoiset
9840607f4b radv: rework and add a helper for hashing a compute pipeline 
It should be similar to the previous hashing method but it allows us
to get a hash directly from a pCreateInfo for future work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28651>
 2024-04-10 20:05:22 +00:00
Samuel Pitoiset
05cd85afc6 radv: add a helper for hashing pipelines 
Similar between graphics/compute/raytracing pipelines.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28651>
 2024-04-10 20:05:22 +00:00
Samuel Pitoiset
c6cb3b3b93 radv/rt: remove dead code about intersection shaders in radv_pipeline_get_shader_key() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28651>
 2024-04-10 20:05:22 +00:00
Sagar Ghuge
7cc604ed1b anv: Fix typo in DestinationAlphaBlendFactor value 
Workaround states that if Destination Alpha Blend
Factor==BLENDFACTOR_ZERO, instead use BLENDFACTOR_CONST_ALPHA with the
constant alpha set to 0.

We had typo while setting the DestinationAlphaBlendFactor, use
BLENDFACTOR_CONST_ALPHA instead of BLENDFACTOR_CONST_COLOR.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28640>
 2024-04-10 19:42:52 +00:00
Georg Lehmann
1f4662cc4e radv: move alu 
The stats are decent now that aco has an ILP scheduler

Foz-DB Navi31:
Totals from 73549 (92.59% of 79439) affected shaders:
MaxWaves: 2226952 -> 2229352 (+0.11%); split: +0.21%, -0.10%
Instrs: 44690384 -> 44905884 (+0.48%); split: -0.10%, +0.58%
CodeSize: 232666088 -> 233474808 (+0.35%); split: -0.10%, +0.45%
VGPRs: 2998036 -> 2986936 (-0.37%); split: -0.58%, +0.21%
SpillSGPRs: 7176 -> 7170 (-0.08%); split: -0.53%, +0.45%
SpillVGPRs: 1124 -> 1068 (-4.98%); split: -5.07%, +0.09%
Scratch: 6981632 -> 6977792 (-0.06%)
Latency: 297998345 -> 298541597 (+0.18%); split: -0.35%, +0.53%
InvThroughput: 49162321 -> 49039572 (-0.25%); split: -0.46%, +0.21%
VClause: 881737 -> 884147 (+0.27%); split: -0.35%, +0.62%
SClause: 1371928 -> 1373973 (+0.15%); split: -0.78%, +0.92%
Copies: 2920492 -> 2927281 (+0.23%); split: -0.84%, +1.08%
Branches: 890209 -> 890121 (-0.01%); split: -0.03%, +0.02%
PreSGPRs: 2376670 -> 2377251 (+0.02%); split: -0.25%, +0.28%
PreVGPRs: 2229634 -> 2208966 (-0.93%); split: -1.04%, +0.11%
VALU: 25124040 -> 25127521 (+0.01%); split: -0.07%, +0.08%
SALU: 4343167 -> 4361062 (+0.41%); split: -0.23%, +0.65%
VMEM: 1582363 -> 1582245 (-0.01%); split: -0.01%, +0.00%
VOPD: 8709 -> 8708 (-0.01%); split: +2.35%, -2.37%

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27032>
 2024-04-10 17:05:59 +00:00
Georg Lehmann
d9a8ab0e01 radv: sink alu 
The stats are decent now that aco has an ILP scheduler.

Foz-DB Navi31:
Totals from 50743 (63.88% of 79439) affected shaders:
MaxWaves: 1504722 -> 1506408 (+0.11%); split: +0.12%, -0.01%
Instrs: 37550246 -> 37543687 (-0.02%); split: -0.12%, +0.10%
CodeSize: 194277496 -> 194253004 (-0.01%); split: -0.11%, +0.10%
VGPRs: 2266056 -> 2254320 (-0.52%); split: -0.57%, +0.06%
SpillSGPRs: 7893 -> 6861 (-13.07%); split: -14.03%, +0.95%
SpillVGPRs: 1359 -> 1124 (-17.29%)
Scratch: 7006720 -> 6981632 (-0.36%)
Latency: 268082325 -> 267597538 (-0.18%); split: -0.57%, +0.39%
InvThroughput: 43592221 -> 43287284 (-0.70%); split: -1.14%, +0.44%
VClause: 759701 -> 761164 (+0.19%); split: -0.24%, +0.43%
SClause: 1133209 -> 1138406 (+0.46%); split: -0.32%, +0.78%
Copies: 2639405 -> 2632081 (-0.28%); split: -0.81%, +0.53%
Branches: 830411 -> 831358 (+0.11%); split: -0.02%, +0.13%
PreSGPRs: 1802510 -> 1798852 (-0.20%); split: -0.57%, +0.36%
PreVGPRs: 1755801 -> 1747642 (-0.46%); split: -0.51%, +0.04%
VALU: 20974500 -> 20967009 (-0.04%); split: -0.08%, +0.04%
SALU: 3901240 -> 3900098 (-0.03%); split: -0.23%, +0.20%
VMEM: 1397890 -> 1397486 (-0.03%)
VOPD: 4837 -> 4902 (+1.34%); split: +2.03%, -0.68%

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27032>
 2024-04-10 17:05:58 +00:00
Peyton Lee
8479c3bddb radeonsi/vpe: add support for p010 
add support for p010, correct the settings of format and buffer pitch.

Signed-off-by: Peyton Lee <peytolee@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28518>
 2024-04-10 16:30:14 +00:00
Christian Gmeiner
d330676c22 etnaviv: Remove offline shader compiler 
This compiler is too limited for the benefit it could bring. A great
replacement for it is shaderdb's runner.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28653>
 2024-04-10 16:09:40 +00:00
David Rosca
fce9a31ba0 frontends/vdpau: Support creating VDP_CHROMA_TYPE_420_16 surfaces 
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28317>
 2024-04-10 15:00:02 +00:00
David Rosca
b17cf67895 frontends/vdpau: Fix cdef strengths and lr_unit_shift in AV1 decode 
Fixes: f9358cb105 ("frontends/vdpau: Add support for VDPAU AV1 decoding.")

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28317>
 2024-04-10 15:00:02 +00:00
Martin Krastev
33785a2ab1 svga/ci: re-enable vmware farm 
Re-enable the farm after an outage. Latter was caused by lava-ci running out
of free space after accumulation of artifacts, mainly docker images. Mend by:

* setting a cronjob for docker system prune --all --volumes
* bumping up lava-ci fs to 128GB

Signed-off-by: Martin Krastev <martin.krastev@broadcom.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28667>
 2024-04-10 14:25:02 +00:00
Hans-Kristian Arntzen
2e502542ac vulkan/runtime: Check correct callback list for binding report. 
instance_callbacks is only used for vkCreateInstance time callbacks.

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Fixes: 34e8e5d76f ("vulkan/debug_utils: add a helper for reporting address binding")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28649>
 2024-04-10 13:50:56 +00:00
Gert Wollny
66066650c9 zink: if AcquireNextImageKHR fails with VK_NOT_READY or VK_TIMEOUT retry 
Gradually increase timeout until we reach a limit on which we abort.
This fixes a crash with

    spec@ext_framebuffer_blit@fbo-blit-check-limits

on llvmpipe.

Fixes: d1cac5ed05
    zink: acquire - maybe clear timeout after waiting for presentation fence

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28558>
 2024-04-10 13:21:43 +00:00
Mike Blumenkrantz
a5a2bd2969 lavapipe: don't clamp index buffer size for null index buffer draws 
this should execute however many draws the user is trying to execute

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28656>
 2024-04-10 12:59:58 +00:00
Jonathan Gray
fef9ad6f66 intel/dev: update DG2 device names 
Ref: 864f42116c/shared/source/dll/devices/devices_base.inl (L53)
Fixes: 98f3d072b4 ("intel/dev: Add 0x56be and 0x56bf DG2 PCI IDs")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28643>
 2024-04-10 12:02:58 +00:00