Commit Graph

107354 Commits

Author SHA1 Message Date
Karol Herbst
cce4955721 gm107/ir: add fp64 rsq
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
2019-02-06 19:35:57 -05:00
Karol Herbst
815a8e59c6 gm107/ir: add fp64 rcp
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
2019-02-06 19:35:57 -05:00
Karol Herbst
12669d2970 gk104/ir: Use the new rcp/rsq in library
[imirkin: add a few more "long" prefixes to safen things up]
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
2019-02-06 19:35:57 -05:00
Boyan Ding
656ad06051 gk110/ir: Use the new rcp/rsq in library
v2: (Karol Herbst <kherbst@redhat.com>
 * fix Value setup for the builtins

Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
[imirkin: track the fp64 flag when switching ops to calls]
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
2019-02-06 19:35:57 -05:00
Boyan Ding
7937408052 gk110/ir: Add rsq f64 implementation
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
2019-02-06 19:35:57 -05:00
Boyan Ding
04593d9a73 gk110/ir: Add rcp f64 implementation
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
2019-02-06 19:35:57 -05:00
Ilia Mirkin
6adb9b38bf nvc0: stick zero values for the compute invocation counts
Not quite perfect, but at least we don't end up with random values in
the query buffer.

Fixes KHR-GL45.pipeline_statistics_query_tests_ARB.functional_default_qo_values

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
2019-02-06 19:35:57 -05:00
Ilia Mirkin
e00799d3dc nv50,nvc0: use condition for occlusion queries when already complete
For the NO_WAIT variants, we would jump into the ALWAYS case for both
nested and inverted occlusion queries. However if the query had
previously completed, the application could reasonably expect that the
render condition would follow that result.

To resolve this, we remove the nesting distinction which unnecessarily
created an imbalance between the regular and inverted cases (since
there's no "zero" condition mode). We also use the proper comparison if
we know that the query has completed (which could happen as a result of
an earlier get_query_result call).

Fixes KHR-GL45.conditional_render_inverted.functional

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
2019-02-06 19:35:57 -05:00
Ilia Mirkin
162352e671 nvc0: fix 3d images on kepler
Looks like SUBFM.3D and SUEAU are perfectly capable of dealing with 3d
tiling, they just need the correct inputs. Supply them.

We also have to deal with the case where a 2d "layer" of a 3d image is
bound. In this case, we supply the z coordinate separately to the
shader, which has to optionally treat every 2d case as if it could be a
slice of a 3d texture.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
2019-02-06 19:35:57 -05:00
Ilia Mirkin
5de5beedf2 nvc0/ir: fix second tex argument after levelZero optimization
We used to pre-set a bunch of extra arguments to a texture instruction
in order to force the RA to allocate a register at the boundary of 4.
However with the levelZero optimization, which removes a LOD argument
when it's uniformly equal to zero, we undid that logic by removing an
extra argument. As a result, we could end up with insufficient alignment
on the second wide texture argument.

Instead we switch to a different method of achieving the same result.
The logic runs during the constraint analysis of the RA, and adds unset
sources as necessary right before being merged into a wide argument.

Fixes MISALIGNED_REG errors in Hitman when run with bindless textures
enabled on a GK208.

Fixes: 9145873b15 ("nvc0/ir: use levelZero flag when the lod is set to 0")
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
2019-02-06 19:35:57 -05:00
Ilia Mirkin
4443b6ddf2 nvc0/ir: always use CG mode for loads from atomic-only buffers
Atomic operations don't update the local cache, which means that we
would have to issue CCTL operations in order to get the updated values.
When we know that a buffer is primarily used for atomic operations, it's
easier to just avoid the caching at that level entirely.

The same issue persists for non-atomic buffers, which will have to be
fixed separately.

Fixes the failing dEQP-GLES31.functional.atomic_counter.* tests.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
2019-02-06 19:35:57 -05:00
Ilia Mirkin
399215eb7a nvc0: add support for handling indirect draws with attrib conversion
The hardware does not natively support FIXED and DOUBLE formats. If
those are used in an indirect draw, they have to be converted. Our
conversion tries to be clever about only converting the data that's
needed. However for indirect, that won't work.

Given that DOUBLE or FIXED are highly unlikely to ever be used with
indirect draws, read the indirect buffer on the CPU and issue draws
directly.

Fixes the failing dEQP-GLES31.functional.draw_indirect.random.* tests.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
2019-02-06 19:35:57 -05:00
Kristian H. Kristensen
0f7a20e91e freedreno/a6xx: Use tiling for all resources
We used to restrict this to just PIPE_BIND_SAMPLER_VIEW resources, but
most resources benefit from being tiled.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-02-06 15:28:48 -08:00
Kristian H. Kristensen
357ea7da51 freedreno/a6xx: Emit blitter dst with OUT_RELOCW
We're writing to the bo and the kernel needs to know for
fd_bo_cpu_prep() to work.

Fixes: f93e431272 ("freedreno/a6xx: Enable blitter")
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
2019-02-06 15:22:25 -08:00
Bas Nieuwenhuizen
13ab63bb62 radv: Implement VK_EXT_buffer_device_address.
v2: Also update the release notes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-02-06 22:37:38 +01:00
Bas Nieuwenhuizen
3259e7b036 radv: Do not use the bo list for local buffers.
The kernel already does it for us.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-02-06 22:36:19 +01:00
Bas Nieuwenhuizen
8a15950211 amd/common: Implement global memory accesses.
Needed for VK_EXT_buffer_device_address.

The pointers are implmemented as i8*, since I could not figure
out how to emulate setting struct offsets in LLVM based on the
SPIR-V offsets (and more weird stuff like row major matrices).

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-02-06 22:36:11 +01:00
Bas Nieuwenhuizen
5703ecf651 amd/common: Do not use 32-bit loads for shared memory.
We use a straight glsl->llvm type conversion so types should already be right.

Also even though the writemasks were changed we we not actually doing 32-bit
things, so this fails miserably.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-02-06 22:36:06 +01:00
Bas Nieuwenhuizen
8d1718590b amd/common: handle nir_deref_cast for shared memory from integers.
Can happen e.g. after a phi.

Fixes: a2b5cc3c39 "radv: enable variable pointers"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-02-06 22:36:02 +01:00
Bas Nieuwenhuizen
830fd0efc1 amd/common: Handle nir_deref_type_ptr_as_array for shared memory.
Fixes: a2b5cc3c39 "radv: enable variable pointers"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-02-06 22:35:58 +01:00
Bas Nieuwenhuizen
dbdb44d575 amd/common: Fix stores to derefs with unknown variable.
Fixes: a2b5cc3c39 "radv: enable variable pointers"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-02-06 22:35:54 +01:00
Bas Nieuwenhuizen
3c24fc64c7 amd/common: Use correct writemask for shared memory stores.
The check was for 1 bit being set, which is clearly not what we want.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-02-06 22:35:49 +01:00
Bas Nieuwenhuizen
00253ab2c4 radv: Fix the shader info pass for not having the variable.
For example with VK_EXT_buffer_device_address or
 VK_KHR_variable_pointers.

Fixes: a2b5cc3c39 "radv: enable variable pointers"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-02-06 22:35:45 +01:00
Bas Nieuwenhuizen
58c8dadd32 amd/common: Implement ptr->int casts in ac_to_integer.
For the implicit casts inherent in nir.

This should probably have been done for shared memory for
VK_KHR_variable_pointers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-02-06 22:35:40 +01:00
Bas Nieuwenhuizen
e00d9a9a72 amd/common: Add gep helper for pointer increment.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-02-06 22:35:36 +01:00
Bas Nieuwenhuizen
39ab4e12f7 radv: Only look at pImmutableSamples if the descriptor has a sampler.
Equivalent of ANV patch c7f4a2867c

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-02-06 22:35:32 +01:00
Eric Engestrom
40b53a7203 xvmc: fix string comparison
Fixes: 6fca18696d "g3dvl: Update XvMC unit tests."
Cc: Younes Manton <younes.m@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 18:15:43 +00:00
Eric Engestrom
110a6e1839 xvmc: fix string comparison
Fixes: c7b65dcaff "xvmc: Define some Xv attribs to allow users
                             to specify color standard and procamp"
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 18:15:43 +00:00
Eric Engestrom
ba26bc4ef0 gitlab-ci: add meson glvnd build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
5459900f38 travis: remove unused scons code path
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
087af992a2 travis: remove unused linux code path
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
73275147fe gitlab-ci: add make Gallium ST Other build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
360a7bfbe9 gitlab-ci: add make Gallium ST Clover LLVM-7 build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
39315a747b gitlab-ci: add make Gallium ST Clover LLVM-6.0 build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
e80f88c48a gitlab-ci: add make Gallium ST Clover LLVM-5.0 build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
cc85f50029 gitlab-ci: add make Gallium ST Clover LLVM-4.0 build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
984e295500 gitlab-ci: add make Gallium ST Clover LLVM-3.9 build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
d0dff24cbb gitlab-ci: add make Gallium Drivers "Other" build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
055cfbc6de gitlab-ci: add make Gallium Drivers RadeonSI build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
7b26a19f31 gitlab-ci: add make Gallium Drivers SWR build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
bbdc563c11 gitlab-ci: add make loaders/classic DRI build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
f33517bda7 gitlab-ci: add meson gallium ST "Other" build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
8dab707ab8 gitlab-ci: add meson gallium ST Clover (LLVM 7.0) build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
8744ac0904 gitlab-ci: add meson gallium ST Clover (LLVM 6.0) build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
b5a70af062 gitlab-ci: add meson gallium ST Clover (LLVM 5.0) build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
d407ead204 gitlab-ci: add meson gallium "other drivers" build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
06e8f1961b gitlab-ci: add meson gallium RadeonSI build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
360c814bfe gitlab-ci: add meson gallium SWR build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
d73265e20d gitlab-ci: add meson loader/classic DRI build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00
Eric Engestrom
6a19ec9daa gitlab-ci: add scons SWR build
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
2019-02-06 17:56:30 +00:00