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Author SHA1 Message Date
Alyssa Rosenzweig
cc8fec8b74 agx: Generate enums from Python 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11199>
 2021-06-05 20:38:22 +00:00
Alyssa Rosenzweig
223476aff3 agx: Model get_sr 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11199>
 2021-06-05 20:38:22 +00:00
Alyssa Rosenzweig
f70068583c asahi: Mark special fragment inputs as sysvals 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11199>
 2021-06-05 20:38:22 +00:00
Alyssa Rosenzweig
c509878971 nir: Add nir_intrinsic_load_back_face_agx 
On AGX, the special register for front facing is inverted from its meaning in
APIs. We need to lower load_front_face to inot(load_back_face). Doing this in
the backend is trivial, but then we would miss out on algebraic optimizations
for the inot.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11199>
 2021-06-05 20:38:22 +00:00
Dmitry Baryshkov
cac88b5f06 freedreno/regs: split old/not used phy registers to separate DB 
In order to simplify main DSI host database, split away phy register
definitions used on DSI v2 hosts to the separate database file.

Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11075>
 2021-06-05 19:20:50 +00:00
Rob Clark
80b1e042e4 freedreno: Don't return a flushed batch 
Somehow fairly recently the traces CI job started hitting timeouts, not
all the time but enough to be inconvenient for CI.  I tracked it down to
getting into a situation where `ctx->batch->flush == true`, which causes
an infinite loop in the draw_vbo and clear paths (because
fd_batch_lock_submit() checks for flushed batch but fd_context_batch()
does not).  I'm not entirely sure how we get into that state, or what
triggered this (seems possibly triggered by !10937).  But it is easy
enough to recover.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11196>
 2021-06-05 18:51:41 +00:00
Rob Clark
ad375d0579 freedreno: Fix typo 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11196>
 2021-06-05 18:51:41 +00:00
Ville Syrjälä
db83dc619c i915: Implement __DRI2_FLUSH version 4 
DRI3 needs version 4 of __DRI2_FLUSH.

Straight up port of i965 commit 313f2bc32b ("intel: Add
support for the new flush_with_flags extension.").

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9734>
 2021-06-05 00:22:22 +00:00
Ville Syrjälä
1c312bfc41 i915: Implement __DRI_IMAGE_ATTRIB_OFFSET query 
DRI3 needs __DRI_IMAGE_ATTRIB_OFFSET so implement it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9734>
 2021-06-05 00:22:22 +00:00
Jason Ekstrand
b742f73913 intel/isl: Fix isl_format_is_valid 
The format enum space isn't necessarily contiguous so we can't assume
that if it's in the table it's valid.  We need to check something.

Fixes: ed6e586562 "intel: properly constify isl_format_layouts"
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11191>
 2021-06-04 16:16:44 -05:00
Hoe Hao Cheng
90a5fef85c nir: define NIR_ALU_MAX_INPUTS 
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11172>
 2021-06-04 19:33:13 +00:00
Emma Anholt
d6d7421e98 util/ra: Use the conflicting neighbor to skip unavailable registers. 
Now that we have an idea of how many regs the conflicting allocation uses,
we can just skip to the next one and save repeated tests to find the same
conflicting neighbor again.

shadowrun-returns shader-db time on skl -1.62821% +/- 1.58079% (n=679),
now there's no statistically significant change from the start of the series
(n=420)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>
 2021-06-04 19:08:57 +00:00
Eric Anholt
23df5dba92 lima: Use ra_alloc_contig_reg_class(). 
This greatly simplifies our register allocation code and reduces the
number of registers RA has to walk over.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>
 2021-06-04 19:08:57 +00:00
Eric Anholt
cf33316ec0 intel/vec4: Use ra_alloc_contig_reg_class() to reduce RA overhead. 
We go from 1672 RA regs to the real 128 HW regs.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>
 2021-06-04 19:08:57 +00:00
Eric Anholt
40e1d798c6 intel/fs: Use ra_alloc_contig_reg_class() to speed up RA. 
By using the new class type, we don't need to make 1928 different
registers to represent each contigous reg size starting from the actual
128 HW register, or have a mapping between RA regs and HW base regs.  With
the number of regs reduced, and the fast q computation when using the new
classes, we no longer need to compute our own q.

This drops the FS RA initialization time on my CFL system from about 1ms to
50us.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>
 2021-06-04 19:08:57 +00:00
Eric Anholt
ec3bc5da74 v3d: Use the ra_alloc_contig_reg_class() function to speed up RA. 
It means we don't need to do the n^2 loop over the regs to set up the pq
values, nor do we need the register conflicts lists.

Acked-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>
 2021-06-04 19:08:57 +00:00
Eric Anholt
15aa8e9189 vc4: Use the ra_alloc_contig_reg_class() function to speed up RA. 
It means we don't need to do the n^2 loop over the regs to set up the pq
values, nor do we need to allocate conflicts lists.

Acked-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>
 2021-06-04 19:08:57 +00:00
Eric Anholt
2d7bcdaf6b ra: Add fast-path support for register classes of contiguous regs. 
In the fully general case of register classes, to expose an allocation
class of unaligned 2-contiguous-regs allocations, for example, you'd have
your base individual regs (128 on intel), and another set of 127 regs that
each conflicted with the corresponding pair of the base regs.  Single-reg
nodes would allocate in the 128, and double-reg nodes would allocate in
the 127 and the user would remap from the 127 down to the base regs with
some irritating table.

If you need many different contiguous allocation sizes (16 is a pretty
common number across drivers), your number of regs explodes, wasting
memory and making the q computation expensive at startup.

If all the user has is contiguous-reg classes, we can easily compute the q
value up front (as found in the intel driver and nouveau, for example),
and we only have to change a couple of places in the conflict-checking
logic so the contiguous-reg classes can use the base registers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>
 2021-06-04 19:08:57 +00:00
Eric Anholt
95d41a3525 ra: Use struct ra_class in the public API. 
All these unsigned ints are awful to keep track of.  Use pointers so we
get some type checking.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>
 2021-06-04 19:08:57 +00:00
Eric Anholt
7e0127fb3e ra: Document that class index is allocated in order, use that in r300. 
etnaviv also relies on this being the case, just drop the remapping.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>
 2021-06-04 19:08:57 +00:00
Eric Anholt
3072318ab8 ra: Add a unit test. 
This is mostly checking that we agree with a bit of the table from the
paper.  It proved quite useful as I was refactoring.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9437>
 2021-06-04 19:08:57 +00:00
Adam Jackson
ed6e586562 intel: properly constify isl_format_layouts 
Putting a const char * in the struct means it's a pointer that has to be
resolved at rtld time, which means it can be in .data.rel.ro but not
.rodata like you'd hope. Fix this with the usual string table trick.

Cuts about 20k (-80k read-write +60k read-only) and ~280 relocations
from the gallium driver.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11168>
 2021-06-04 18:32:33 +00:00
Mike Blumenkrantz
8fb1300333 zink: explicitly advertise index buffer format support 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11132>
 2021-06-04 17:57:03 +00:00
Mike Blumenkrantz
c011e6061d d3d12: explicitly advertise index buffer format support 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11132>
 2021-06-04 17:57:03 +00:00
Erik Faye-Lund
aea35a5ac2 r600: explicitly advertise index buffer format support 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11132>
 2021-06-04 17:57:03 +00:00
Mike Blumenkrantz
de9c66d749 r300: explicitly advertise index buffer format support 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11132>
 2021-06-04 17:57:03 +00:00
Mike Blumenkrantz
cc99c1c762 nouveau: explicitly advertise index buffer format support 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11132>
 2021-06-04 17:57:03 +00:00
Emma Anholt
842c514303 llvmpipe: Don't call util_init_math(). 
Nothing in llvmpipe uses util_fast_log2().

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11173>
 2021-06-04 17:26:28 +00:00
Emma Anholt
9cd4b8b73c u_math: Reduce fast-log2 table size from 65k entries back to 256. 
This was bumped in 7e584a70c4 ("gallium: increase table size for fast
log/pow functions") presumably to fix conformance of tgsi_exec, but we
don't need that much accuracy in the only place it's used in the tree any
more: softpipe texture sampling.

softpipe glmark2 -b texture:texture-filter=linear FPS +0.335748% +/-
0.220111% (n=20)

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11173>
 2021-06-04 17:26:28 +00:00
Emma Anholt
fd3f9eedbe tgsi_exec: Garbage-collect the FAST_MATH path. 
It's disabled due to non-conformance with no configuration knob to turn it
on, and if you care about swrast performance you're on llvmpipe anyway.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11173>
 2021-06-04 17:26:28 +00:00
Mike Blumenkrantz
2ee030e45c Revert "Revert "zink: call tc_driver_internal_flush_notify() on flush"" 
This reverts commit 9ff54d408b.

this is fine now that tc unbinds are fixed

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11187>
 2021-06-04 17:05:47 +00:00
Mike Blumenkrantz
535a5a9dfe aux/tc: fix ubo unbinding 
unsetting a ubo requires an unbind

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11187>
 2021-06-04 17:05:47 +00:00
Daniel Schürmann
d4662e38c4 aco: simplify Phi RegClass selection 
Also adds moves validation rules to aco_validate.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11181>
 2021-06-04 16:47:01 +00:00
Daniel Schürmann
dc807dff3e radv,aco: scalarize all phis via nir_lower_phis_to_scalar() 
This allows to remove some ACO code which did so previously.

Totals from 93 (0.06% of 149839) affected shaders (Navi2):
CodeSize: 582424 -> 582348 (-0.01%); split: -0.10%, +0.08%
Instrs: 107083 -> 107011 (-0.07%); split: -0.08%, +0.01%
Latency: 483338 -> 484881 (+0.32%); split: -0.09%, +0.40%
InvThroughput: 101129 -> 101532 (+0.40%); split: -0.03%, +0.42%
Copies: 9893 -> 9774 (-1.20%); split: -1.28%, +0.08%
Branches: 2862 -> 2858 (-0.14%)
PreSGPRs: 3342 -> 3339 (-0.09%)
PreVGPRs: 4567 -> 4565 (-0.04%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11181>
 2021-06-04 16:47:01 +00:00
Marek Olšák
057a702a3f st/mesa: execute glFlush asynchronously if no image has been imported/exported 
This improves viewperf performance and it shouldn't break synchronization
with external clients when it's indirectly implied by glFlush.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10937>
 2021-06-04 15:58:25 +00:00
Mike Blumenkrantz
4304a7adc7 zink: use VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL when possible 
this is allowed for fb attachments, so we can use it to avoid needing to
change layouts for zs textures if we know that it isn't going to be written
to during a given subpass

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11130>
 2021-06-04 15:10:11 +00:00
Mike Blumenkrantz
3f332b16d5 zink: track number of fb attachment binds on resources 
this will be useful for applying layouts

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11130>
 2021-06-04 15:10:11 +00:00
Mike Blumenkrantz
9a1c833841 zink: emit fb attachment barriers inline during renderpass start 
we don't need a separate function for this

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11130>
 2021-06-04 15:10:11 +00:00
Samuel Pitoiset
b786c16365 radv/winsys: allow to reserve a VMID 
This will be used by SPM and also for configuring the trap handler.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11128>
 2021-06-04 14:53:25 +00:00
Danylo Piliaiev
20d8324a1b turnip: implement VK_EXT_provoking_vertex 
Passes: dEQP-VK.rasterization.provoking_vertex.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11112>
 2021-06-04 14:37:01 +00:00
Rhys Perry
49add985ff nir/unsigned_upper_bound: don't require dominance metadata 
Instead, determine if it's a merge or loop exit phi.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9808>
 2021-06-04 14:14:00 +00:00
Rhys Perry
aebffc241d aco: don't use nir_block_is_unreachable() 
nir_cf_reinsert() can re-create the block, invalidating dominance
metadata.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9808>
 2021-06-04 14:14:00 +00:00
Mike Blumenkrantz
ef2e29f3b5 zink: no-op read access buffer barriers if existing access exists for earlier stage 
only the earliest stage should be applied for these barriers, so we can skip
ones where the existing access is earlier

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11131>
 2021-06-04 13:52:33 +00:00
Tapani Pälli
cbaba3f1b9 docs: add VK_EXT_extended_dynamic_state2 features.txt entry 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10366>
 2021-06-04 12:58:34 +00:00
Tapani Pälli
0d031d1da3 anv: toggle on VK_EXT_extended_dynamic_state2 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10366>
 2021-06-04 12:58:34 +00:00
Tapani Pälli
75ad0e4b08 anv: support blending logic op dynamic state 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10366>
 2021-06-04 12:58:34 +00:00
Tapani Pälli
e0c6055351 anv: centralize vk_to_intel_logic_op array 
This avoids multiple copies as we will need this in multiple places.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10366>
 2021-06-04 12:58:34 +00:00
Tapani Pälli
1c718952c8 anv: support primitive restart enable dynamic state 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10366>
 2021-06-04 12:58:34 +00:00
Tapani Pälli
496b508403 anv: support depth bias enable dynamic state 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10366>
 2021-06-04 12:58:34 +00:00
Tapani Pälli
4d531c67df anv: support rasterizer discard dynamic state 
Implemented by emitting 3DSTATE_STREAMOUT packet.

v2: logic fixes + merge and emit properly all contents (Lionel)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10366>
 2021-06-04 12:58:34 +00:00