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Author SHA1 Message Date
Marek Olšák
5f4659260e radeonsi/gfx9: ELEMENT_SIZE change 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
d214b95e9a radeonsi/gfx9: enable ETC2 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
6d21fd51b6 radeonsi/gfx9: disable RB+ on Vega10 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
2862300d9e radeonsi/gfx9: init_config changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
b054718218 radeonsi/gfx9: don't set PA_SC_RASTER_CONFIG* 
The registers don't exist on GFX9.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
de7967a27a radeonsi/gfx9: Gather4 no longer needs the workaround 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
71ad666414 radeonsi/gfx9: CP DMA changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
7690196135 radeonsi/gfx9: query changes - EVENT_WRITE and SET_PREDICATION 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
ea9cf0a322 radeonsi/gfx9: EVENT_WRITE_EOP -> RELEASE_MEM 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
3e3d4f5e1d radeonsi/gfx9: INDIRECT_BUFFER change 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
9680a75489 radeonsi/gfx9: enable SDMA buffer copying & clearing 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
c9b004af58 radeonsi/gfx9: handle GFX9 in a few places 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
92112ec296 radeonsi/gfx9: don't read back non-existent SRBM registers 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
ef97cc0cae radeonsi/gfx9: add IB parser support 
Both GFX6 and GFX9 fields are printed next to each other in parsed IBs.

The Python script parses both headers like one stream and tries to merge
all definitions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
9338ab0afd radeonsi/gfx9: set the LLVM processor, require LLVM 5.0 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
68d6d097f1 radeonsi/gfx9: add GFX9 and VEGA10 enums 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
5691e14735 amd: GFX9 packet changes 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
ecbdfbeb05 amd: define event types for GFX9 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
00e777b61c amd: add texture format definitions for GFX9 
the DATA_FORMAT and NUM_FORMAT fields are the same, but some of the enums
differ, thus add GFX6 and GFX9 suffixes, so that the IB parser can show
enums for both.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
e6c520362d amd: resolve remaining definition conflicts with gfx9d.h 
Add _GFX6 and _GFX9 suffixes to conflicting definitions.

sid.h and gfx9d.h can now be included in the same file.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
7e7043c31c amd: normalize register definition formatting 
This resolves trivial conflicts with gfx9d.h caused by different formatting.
Some fields are also renamed.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
db04d4ccaa amd: import GFX9 register definitions 
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
a3556c0f06 radeonsi: code shuffling in si_init_depth_surface 
use fewer local variables, re-order the assignments, so that the GFX9 diff
is smaller here.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Marek Olšák
8a74140a21 amd/addrlib: silence warnings 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
7f160efcde amd/addrlib: import gfx9 support 2017-03-30 14:44:33 +02:00
Kevin Furrow
047d6daf10 amd/addrlib: Not all ETC2 formats are 128bpp... add new ETC2 formats to differentiate between 64 and 128bpp formats. 2017-03-30 14:44:33 +02:00
Kevin Furrow
1360018c1c amd/addrlib: Fix selection of swizzle modes for 3D compressed images. 2017-03-30 14:44:33 +02:00
Kevin Furrow
9705e3b72c amd/addrlib: Add support for ETC2 and ASTC formats. 2017-03-30 14:44:33 +02:00
Joe Ma
a489cdb20f amd/addrlib: Bump version to 6.02 2017-03-30 14:44:33 +02:00
Frans Gu
e736edf63d amd/addrlib: Adjust slie size after pitch and actual height adjustment 2017-03-30 14:44:33 +02:00
Frans Gu
588e5bbf3d amd/addrlib: Apply input pitch after internal pitch aligning 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
11f1306207 amdgpu/addrlib: Bump version to 6.01 
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
a136926eef amdgpu/addrlib: Seperate 2 dcc related workarounds by different flags 
1) dccCompatible for padding MSAA surface to support fast clear
2) dccPipeWorkaround for padding surface to support dcc
 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
48bf5d0800 amdgpu/addrlib: Fix the issue that tcCompatible HTILE slice size is not calculated correctly 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
33c25655c1 amdgpu/addrlib: Add a new output flag to notify client that the returned tile index is for PRT on SI 
If this flag is set for mip0, client should set prt flag for sub mips,
so that address lib can select the correct tile index for sub mips.
 2017-03-30 14:44:33 +02:00
Xavi Zhang
fa906a888b amdgpu/addrlib: add matchStencilTileCfg and tcCompatible fixes 
The usage should be client first call AddrComputeSurfaceInfo() on
depth surface with flag "matchStencilTilecfg", AddrLib will use
2DThin1 tile index for depth as much as possible and do not down grade
unless alignment requirement cannot be met.

1. If there is a matched 2DThin1 tile index for stencil which make
sure they will share same tile config parameters, then return the
stencil 2DThin1 tile index as well.
2. If using 2DThin1 tile mode cannot make sure such thing happen, and
TcCompatible flag was set, then ignore this flag then try 2DThin1 tile
mode for depth and stencil again.
3. If 2DThin1 tile mode cannot make sure depth and stencil to have
same tile config parameters, then down grade depth surface tile mode
to 1DThin1.
4. If depth surface's tile mode was 1DThin1, then return 1DThin1 tile
index for stencil.
5. If depth surface's tile mode is PRT, then return invalid tile index
to stencil since their tile config parameters will never be met.

Client driver then check the returned tile index of stencil -- if it
is not invalid tile index, then call AddrComputeSurfaceInfo() on
stencil surface with the returned stencil tile index to get full
output information. Please note, client needs to set flag
"useTileIndex" when AddrLib get created.
 2017-03-30 14:44:33 +02:00
Frans Gu
6764d96eaa amdgpu/addrlib: Adjust bank equation bit order based on macro tile aspect ratio settings 
By this way, we can have valid equation for 2D_THIN1 tile mode.
Add flag "preferEquation" to return equation index without adjusting
input tile mode.
 2017-03-30 14:44:33 +02:00
Frans Gu
ed1aca8e8f amdgpu/addrlib: do some tile mode conversions to display surface 2017-03-30 14:44:33 +02:00
Xavi Zhang
cb8844392c amdgpu/addrlib: Check prt flag for PRT_THIN1 extra padding for DCC. 2017-03-30 14:44:33 +02:00
Frans Gu
fe216415c6 amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlign 
1) minimizePadding - Use 1D tile mode if padded size of 2D is bigger
than 1D
2) maxBaseAlign - Force PRT tile mode if macro block size is bigger than
requested alignment.

Also, related changes to tile mode optimization for needEquation.
 2017-03-30 14:44:33 +02:00
Xavi Zhang
4dd4700612 amdgpu/addrlib: Always returns pixelPitch in original pixels 2017-03-30 14:44:33 +02:00
Sabre Shao
eb3036ed46 amdgpu/addrlib: fix crash on allocation failure 2017-03-30 14:44:33 +02:00
Frans Gu
680f91e5d4 amdgpu/addrlib: Add flag to report if a surface can have dcc ram 2017-03-30 14:44:33 +02:00
Roy Zhan
ca88f83222 amdgpu/addrlib: support non-power2 height alignment (for linear surface) 2017-03-30 14:44:33 +02:00
Frans Gu
c867a2b222 amdgpu/addrlib: Fix family setting for VI and CZ ASICs 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
b328e47d3d amdgpu/addrlib: style cleanup 
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
fbc9ba7559 amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on Fiji 
The change also modifies function CiLib::HwlPadDimensions to report
adjusted pitch alignment.
 2017-03-30 14:44:33 +02:00
Xavi Zhang
145750efba amdgpu/addrlib: Fix number of // 
Find ^/{80,99}$  and replace them to 100 "/"

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
4e2668ecd1 amdgpu/addrlib: Cleanup. 
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00
Xavi Zhang
d1ecb70ba3 amdgpu/addrlib: Use namespaces 
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2017-03-30 14:44:33 +02:00