Commit Graph

176217 Commits

Author SHA1 Message Date
Lionel Landwerlin
c87d5c67d9 anv: implement VK_EXT_pipeline_robustness
v2:
 - Use vk_pipeline_robustness_state

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>
2023-08-09 09:03:45 +03:00
Lionel Landwerlin
9934613c74 anv/hasvk: track robustness per pipeline stage
And split them into UBO and SSBO

v2 (Lionel):
 - Get rid of robustness fields in anv_shader_bin
v3 (Lionel):
 - Do not pass unused parameters around

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>
2023-08-09 09:00:12 +03:00
Lionel Landwerlin
c4ec60e87d hasvk: remove descriptor array bounds checking
Same reason as Anv.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>
2023-08-09 09:00:12 +03:00
Lionel Landwerlin
059e82a469 anv: remove descriptor array bounds checking
We cannot find anything in the Vulkan spec requiring this. D3D12 [1]
says it's undefined as long as it doesn't crash the OS :

   "Out of bounds indexing of any descriptor table from the shader
    results in a largely undefined memory access, including the
    possibility of reading arbitrary in-process memory as if it is a
    hardware state descriptor and living with the consequence of what
    the hardware does with that. This could produce a device reset, but
    will not crash Windows."

[1] : https://learn.microsoft.com/en-us/windows/win32/direct3d12/advanced-use-of-descriptor-tables#out-of-bounds-indexing

Found 2 titles affected by this change

Some pretty good results on Cyberpunk 2077 :

  Totals from 10285 (100.00% of 10285) affected shaders:
  Instrs: 7638709 -> 7517360 (-1.59%); split: -1.64%, +0.05%
  Cycles: 148047414 -> 148470916 (+0.29%); split: -0.83%, +1.12%
  Subgroup size: 112544 -> 112576 (+0.03%); split: +0.04%, -0.01%
  Spill count: 98 -> 90 (-8.16%)
  Fill count: 90 -> 82 (-8.89%)
  Max live registers: 495274 -> 479502 (-3.18%); split: -3.21%, +0.03%
  Max dispatch width: 87824 -> 91168 (+3.81%); split: +4.10%, -0.29%

  Gaining 297 shaders in SIMD16/32, loosing 16 SIMD32 shaders

Some not so good results on Strange Brigade :

  Totals from 4027 (100.00% of 4027) affected shaders:
  Instrs: 2080355 -> 2013880 (-3.20%); split: -3.20%, +0.01%
  Cycles: 25405149 -> 25170579 (-0.92%); split: -1.37%, +0.45%
  Max live registers: 167303 -> 168958 (+0.99%)
  Max dispatch width: 33264 -> 32496 (-2.31%)

  Loosing 96 SIMD16 shaders.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>
2023-08-09 09:00:12 +03:00
Lionel Landwerlin
0e5b4b1b43 hasvk: fix null descriptor handling with A64 messages
This replicates the same fix we did for Anv and null descriptors with
A64 messages from commit efcda1c530 ("anv: fix null descriptor
handling with A64 messages").

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>
2023-08-09 09:00:12 +03:00
Yonggang Luo
8fe6e6957c svga: use alignas over struct MKSGuestStatInfoEntry
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24571>
2023-08-09 05:15:09 +00:00
Yonggang Luo
0ca43db2d0 v3dv: Use alignas(8) over 64 bit atomic value
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24571>
2023-08-09 05:15:09 +00:00
Yonggang Luo
d130c96bda util/treewide: Use alignas(x) instead __attribute__((aligned(x)))
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24571>
2023-08-09 05:15:09 +00:00
Thomas H.P. Andersen
8c25cd307a nvk: EXT_conditional_rendering
This reads the buffer value, combines it with the inverted setting
and sets SET_RENDER_ENABLE depending on this.

This works for draw and clear calls, but not for dispatch.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24520>
2023-08-09 04:11:50 +00:00
Dave Airlie
07c70c77de nvk: add cond render upload buffer.
conditional render has some issues with vram, so we have to use
a gart buffer to put the value into. This is similiar to what
nvidia seem to do.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24520>
2023-08-09 04:11:50 +00:00
Dave Airlie
fbe171638e nvk: add gart forced cmd pool side buffer.
Currently we put the upload and cmd bos into GART, however in the
future this might change, but for conditional rendering we must have
 a GART space to read the value from. This creates a separate buffer
allocations that are gart forced. This will be used to provide
cond render with a gart location.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24520>
2023-08-09 04:11:50 +00:00
Timothy Arceri
92c5460253 glsl: mark structs containing images as bindless
Structs are not allowed to contain an image in regular glsl. The only time
they are intended to be allowed to be declared in a struct is when
they are bindless.

Unfortunately the bindless spec does not meantion this behaviour
explicitly so there is no spec quote to reference but you can see in
the original commit to allow them in mesa that spec clarification was
provided 48b7882200

The spec also states that certain uses are implicitly bindless as per
the following spec quote:

   "When used as shader inputs, outputs, uniform block members,
   or temporaries, the value of the sampler is a 64-bit unsigned
   integer handle and never refers to a texture image unit."

Given images are not allowed in regular glsl for the above types
similair to being forbidden in structs, we can also assume
declarations in structs are implicitly bindless.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24269>
2023-08-09 01:27:58 +00:00
Mike Blumenkrantz
8dd2691020 aux/trace: fix winsys handle dumping
cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24493>
2023-08-08 23:54:29 +00:00
Mike Blumenkrantz
f1db28da35 zink: add VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT
now that there's more locking around pipeline caches this makes sense

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24559>
2023-08-08 23:13:46 +00:00
Mike Blumenkrantz
1c1e09249c zink: add more locking for pipeline cache
this ensures the size remains constant for entry updates

fixes #9494

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24559>
2023-08-08 23:13:46 +00:00
Mike Blumenkrantz
eea408e563 zink: use SPV_KHR_workgroup_memory_explicit_layout when available
aliasing shared memory is otherwise questionably legal

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24467>
2023-08-08 21:20:05 +00:00
Mike Blumenkrantz
904cf2329b zink: propagate have_workgroup_memory_explicit_layout to ntv
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24467>
2023-08-08 21:20:05 +00:00
Mike Blumenkrantz
ae3163dfd2 zink: hook up VK_KHR_workgroup_memory_explicit_layout
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24467>
2023-08-08 21:20:05 +00:00
George Ouzounoudis
0bb55b4634 nvk: Enable dynamic line rasterization mode state
Enables extendedDynamicState3LineRasterizationMode feature.
Just moved the state flipping from the pipeline to the dynamic rs state
flush.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24517>
2023-08-08 20:45:31 +00:00
georgeouzou
870636cc1f nvk: Support VK_EXT_line_rasterization
- bresenham and smooth lines

These two need to override multisample rasterization to get correct
results on CTS tests.

- stippled lines

The stipple factor needs to be remapped from [1, 256] to [0, 255].

-rectangular and strict lines

Rectangular lines need multisample rasterization rules to get correctly
rasterized even for one sample. That way we get strict lines too for
VK_LINE_RASTERIZATION_MODE_DEFAULT_EXT.

As per the DX rasterization rules:

Rasterization rules for primitives are, in general, unchanged by multisample antialiasing, except:
- For a triangle, a coverage test is performed for each sample location (not for a pixel center).
  If more than one sample location is covered, a pixel shader runs once with attributes interpolated at the pixel center.
  The result is stored (replicated) for each covered sample location in the pixel that passes the depth/stencil test.
- A line is treated as a rectangle made up of two triangles, with a line width of 1.4.
- For a point, a coverage test is performed for each sample location (not for a pixel center).

For single sample rasterization we get the same results for the
triangles and points, but for lines we get the rectangular form instead.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24517>
2023-08-08 20:45:31 +00:00
Mike Blumenkrantz
cf8fe9baec zink: set msrtss depth resolve mode when enabled
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24309>
2023-08-08 20:20:09 +00:00
Mike Blumenkrantz
2630a89b72 zink: don't append msrtss to dynamic render if not supported
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24309>
2023-08-08 20:20:09 +00:00
Mike Blumenkrantz
751407a59a zink: don't add VK_IMAGE_USAGE_ATTACHMENT_FEEDBACK_LOOP_BIT_EXT for transient images
this is illegal

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24309>
2023-08-08 20:20:09 +00:00
Mike Blumenkrantz
300cbedc78 zink: fix zs resolve attachment indexing
this has never been tested until now

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24309>
2023-08-08 20:20:09 +00:00
Mike Blumenkrantz
5ac2291c6b zink: add batch refs for transient images
ensure these don't get deleted while in use

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24309>
2023-08-08 20:20:09 +00:00
Tatsuyuki Ishi
e1e813586c radv/winsys: Remove unused struct radv_winsys_bo_list.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24551>
2023-08-08 19:24:10 +00:00
Tatsuyuki Ishi
b85817f877 radv/amdgpu: Remove unused bo_list variable from cs_submit.
Handle based bo_list is no longer used since 767a9324b9 ("radv/amdgpu:
remove legacy code path for creating the BO list").

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24551>
2023-08-08 19:24:10 +00:00
Emma Anholt
371c18b331 freedreno/a5xx: Skip SSBO emit when none are enabled.
There was a weird NUM_UNIT=0 in a crash dump I was looking at, but this
doesn't fix the crash.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:59 +00:00
Emma Anholt
e9a6832a1b freedreno: Fix crashdec pre-a6xx.
We'd assert fail looking up the REM registers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:59 +00:00
Emma Anholt
33f2726b97 ci/freedreno: Add a regression test for decoding a540 blob's compute shaders.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:59 +00:00
Eric Anholt
b10f4eda70 freedreno/cffdec: Fix decode on pixel 2 blob's COMPUTE_CHECKPOINT
dEQP-GLES31.functional.image_load_store.buffer.image_size.writeonly_7
produces:

t7		opcode: CP_COMPUTE_CHECKPOINT (6e) (8 dwords)
			{ ADDR_0_LO = 0x15000 }
			{ ADDR_0_HI = 0x5 }
			0x18
			{ ADDR_1_LEN = 3 }
			0xf
			{ ADDR_1_LO = 0x2e010 }
			{ ADDR_1_HI = 0x5 }

and it was asserting due to sizedwords==7.  Without the assert, we were
dereffing a len past the end of the packet.  This len value we were
loading is also suspiciously not the location of the ADDR_1_LEN field in
the packet's XML.  But then, the command stream at ADDR_1 was clearly 0xf
long, and that puts ADDR_1_LEN at the spot we would expect compared to
SET_RENDER_MODE's ADDR_1.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:59 +00:00
Emma Anholt
f7bd10ed38 freedreno/a5xx: Add private mem support.
A bunch of our piglit fails were due to failing to compile shaders due to
a lack of spilling support.  I used a simple shader with a large local
array with tunable size to determine the MEMSIZEPERITEM increment and the
location of HWSTACKOFFSET (matching a3xx locations).  Unfortunately
fibers_per_sp I had to guess by taking a big spilling shader and cranking
it up until it rendered correctly.  The value I found made HWSTACKOFFSET's
shift value match a6xx's, as a bit of confirmation.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:59 +00:00
Emma Anholt
c4874b4cee freedreno/a5xx: Set num_sp_cores and set PC/VFD_POWER_CNTL accordingly.
Based on libwrap tracing of the blob.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:59 +00:00
Emma Anholt
c9f9d71412 freedreno/a5xx: Refactor SHADER_OBJ emit to a helper function.
This will grow private mem setup shortly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:59 +00:00
Emma Anholt
c361e1d0d9 freedreno/a3xx: Add the shift for MEMSIZEPERITEM according to db410c docs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:59 +00:00
Emma Anholt
0fb797aab0 freedreno/a6xx: Move pvtmem allocation to ir3_gallium.
This will be the same thing for pre-a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:59 +00:00
Emma Anholt
a4c89cc8a6 freedreno/devices: Set num_sp_cores explicitly for pre-gen6.
These are all 0 currently, but will change for a5xx shortly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:58 +00:00
Emma Anholt
f6ea7c3a99 freedreno/devices: Move fibers_per_sp to the common info struct.
We'll need it for pvt mem on other GPUs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:58 +00:00
Emma Anholt
b468286937 ci/freedreno: Add some more db820c xfails.
We do a fractional run so we didn't have them listed.  Adding these helps
me with local baseline testing, and future people doing uprevs or
rebalancing.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:58 +00:00
Emma Anholt
bdeadc366a ci/freedreno: Update comments for some a530 xfails.
That assert doesn't exist any more but the test still fails.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:58 +00:00
Emma Anholt
0918b90987 ci/freedreno: Sort another a530 xfail with its friends.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:58 +00:00
Emma Anholt
9cfa86202e ci/freedreno: Drop a bunch of stale a530 xfails.
These all pass fairly reliably on my a530 when run on their own.  We've
not noticed this because a530 has some very loose flakes regexes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:58 +00:00
Emma Anholt
e3274e9e1b freedreno/ir3: Move pvtmem per-fiber size alignment to the compiler.
Instead of having tu and each fd backend do it.  This will help me make
some shared code on freedreno for pre-6xx pvtmem support.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:58 +00:00
Emma Anholt
a297624182 freedreno/a5xx: Skip emitting unused texture descriptors for images.
In that case, we'd emit it to DST_OFF=255+i, angering the hardware
mightily.  This was missed in the addition of a6xx image support.

Fixes: 2e0ea3f09c ("freedreno/ir3: add image/ssbo <-> ibo/tex mapping")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:58 +00:00
Emma Anholt
59e9909cc1 freedreno/a5xx: Fix border color structure size.
This now matches a6xx.  This major border color flakiness in deqp -- when
a prior test in the caselist bound a VS and it didn't get unbound at the
gallium level, our FS border colors would be up at offset 8 instead of 0,
and the wrong padding would make FS sampler 0 get a junk border color.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>
2023-08-08 18:51:58 +00:00
Samuel Pitoiset
1b66ebf09a radv/rt: fix capture/replay support
When replaying a RT pipeline, RADEON_FLAG_REPLAYABLE should be set.

The idea is that for capture, RADEON_FLAG_REPLAYABLE should be passed
when allocating a BO (ie. replay_va would be 0), and then for replay
the VA would be non-zero but the flag is also required.

Fixes
dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.multithreaded_compilation.*.

Fixes: 744357477e ("radv: Add utilities to serialize and deserialize shader allocation info")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24543>
2023-08-08 18:07:22 +00:00
Sagar Ghuge
12be0829ea docs: Add INTEL_DEBUG_BKP_BEFORE/AFTER_DRAW_COUNT
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24308>
2023-08-08 17:36:20 +00:00
Sagar Ghuge
f575d4bc6f blorp: Implement blorp hooks to emit breakpoint
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24308>
2023-08-08 17:36:19 +00:00
Sagar Ghuge
1e3b40ffcf iris: Add GPU breakpoint before/after draw call
This change allow us to insert the MI_SEMAPHORE_WAIT before/after
specific draw call. With GTX tool, we can always update the memory
address to unblock spinning wait.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24308>
2023-08-08 17:36:19 +00:00
Sagar Ghuge
49eabb9ea6 anv: Add GPU breakpoint before/after specific draw call
This change allow us to insert the MI_SEMAPHORE_WAIT before/after
specific draw call. With GTX tool, we can always update the memory
address to unblock spinning wait.

v2:
- Make sure draw_call_count is thread-safe (Lionel)
- Add static inline helper (Lionel)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24308>
2023-08-08 17:36:19 +00:00