Commit Graph

83316 Commits

Author SHA1 Message Date
Anuj Phogat
c7b787ef90 Revert "docs: Mark KHR_texture_compression_astc_sliced_3d done on i965"
This reverts commit 82f8c23950.

KHR_texture_compression_astc_sliced_3d is not a requirement for
GLES 3.2.

Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>\
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-07-18 15:43:58 -07:00
Anuj Phogat
82f8c23950 docs: Mark KHR_texture_compression_astc_sliced_3d done on i965
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-07-18 14:39:54 -07:00
Anuj Phogat
ac0eb36d8e i965/gen9: Enable KHR_texture_compression_astc_sliced_3d
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-07-18 14:39:54 -07:00
Anuj Phogat
15dea5ca82 mesa: Add the infrastructure for KHR_texture_compression_astc_sliced_3d
V2: Drop the changes to gl.xml.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-07-18 14:39:54 -07:00
Christian König
3e1ad846f9 radeon/uvd: add session context buffer for polaris 10/11 v2
This way we have unlimited UVD sessions.

v2: only enable it when kernel supports it as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-18 17:13:17 +02:00
Leo Liu
134d6e4e4f vl/dri3: fix a memory leak from front buffer
Inspired by fix for mem leak of vdpau interop, resource_from_handle
set texture reference count, that need to be decreased and released,
recall there is a similar case for DRI3, that is with VA-API glx
extension, there is temporary TFP(texture from pixmap), we target it
through dma-buf. leak happens when without count down the reference.

Checked and found with mpv vo=opengl case, there only one static TFP,
the leak happens once, but for totem player using gstreamer VA-API glx,
the dynamic TFP for each frame, so leak quite a bit.

This fixes mem leak for mpv and totem.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
2016-07-18 09:20:40 -04:00
Iago Toral Quiroga
0f2516d88f i965/tes/scalar: fix 64-bit indirect input loads
We totally ignored this before because there were no piglit tests for
indirect loads in tessellation stages with doubles.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-07-18 09:53:51 +02:00
Iago Toral Quiroga
1737e75bfb i965/tcs/scalar: only update imm_offset for second message in 64bit input loads
Our indirect URB read messages take both a direct and an indirect offset
so when we emit the second message for a 64-bit input load we can just
always incremement the immediate offset, even for the indirect case.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-07-18 09:53:16 +02:00
Kenneth Graunke
18f67c8a69 i965: Move pulls_bary setting to emit_pixel_interpolator_send().
pulls_bary should be set when the shader uses a pixel interpolator
message.  So, setting it from the function that emits pixel interpolator
messages makes a lot of sense.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-07-17 19:26:54 -07:00
Kenneth Graunke
7ef7738a61 i965: Write gl_FragCoord directly to the destination.
This patch makes emit_general_interpolation take a destination register
as an argument, and write directly to that.  This is simpler than the
old approach of ralloc'ing a register, writing to that temporary, and
then making the caller emit per-component MOVs to copy it to the actual
destination.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-07-17 19:26:53 -07:00
Kenneth Graunke
a03812c321 i965: Drop has_pln checks in unlit centroid workaround.
The unlit centroid workaround starts being necessary on Gen6, which
is the first platform with multisampling.  PLN exists on G45+, so all
platforms which need this workaround have PLN.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-07-17 19:26:53 -07:00
Kenneth Graunke
b94890c19f i965: Drop VARYING_SLOT_FACE special case in barycentric setup.
glsl_to_nir always produces a system value for gl_FrontFacing, rather
than an input.  So there should never be an input with this slot,
making this code dead.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-07-17 19:26:53 -07:00
Kenneth Graunke
ac1181ffbe compiler: Rename INTERP_QUALIFIER_* to INTERP_MODE_*.
Likewise, rename the enum type to glsl_interp_mode.

Beyond the GLSL front-end, talking about "interpolation modes" seems
more natural than "interpolation qualifiers" - in the IR, we're removed
from how exactly the source language specifies how to interpolate an
input.  Also, SPIR-V calls these "decorations" rather than "qualifiers".

Generated by:
$ find . -regextype egrep -regex '.*\.(c|cpp|h)' -type f -exec sed -i \
  -e 's/INTERP_QUALIFIER_/INTERP_MODE_/g' \
  -e 's/glsl_interp_qualifier/glsl_interp_mode/g' {} \;

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Dave Airlie <airlied@redhat.com>
2016-07-17 19:26:48 -07:00
Dave Airlie
e7d96e7685 virgl: drop pointless leftover init of virgl_transfer_inline_write.
Pointed out by Marek.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-07-17 06:20:53 +10:00
Ilia Mirkin
062c6b8e54 nv50: fix alphatest for non-blendable formats
The hardware can only do alphatest when using a blendable format. This
means that the various *16 norm formats didn't work with alphatest. It
appears that Talos Principle uses such formats, as well as alpha tests,
for some internal renders, which made them be incorrect. However this
does not appear to affect the final renders, but in a different game it
easily could.

The approach we take is that when alphatests are enabled and a suitable
format is used (which we anticipate is the vast minority of the time),
we insert code into the shader to perform the comparison and discard.
Once inserted, that code lives in the shader forever, and we re-upload
it each time the function changes with a fixed-up compare. To avoid
re-uploading too often, if we switch back to a blendable format, the
test is (effectively) disabled and the hw alphatest functionality is
used.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-16 11:45:30 -04:00
Rob Clark
cc46fc3c09 mesa/st: reduce size of state->st bitmask
In d035d50 this changed to 64b.. which I'm pretty sure was
unintentional.  Revert it back to 32b so the entire state struct
is a nice round 64b.

(Note sure that it would actually be measurable, but I did notice
that check_state() was hot in some benchmarks.)

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-16 10:00:04 -04:00
Rob Clark
44bbfedbd9 gallium/u_queue: add optional cleanup callback
Adds a second optional cleanup callback, called after the fence is
signaled.  This is needed if, for example, the queue has the last
reference to the object that embeds the util_queue_fence.  In this
case we cannot drop the ref in the main callback, since that would
result in the fence being destroyed before it is signaled.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-07-16 10:00:04 -04:00
Nicolai Hähnle
6f73c7595f radeonsi: remove the DRAW_PREAMBLE packet
According to firmware guys, the new sequence that we added for Polaris should
work on all CIK parts, and should actually be faster on some parts.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-16 13:02:37 +02:00
Brian Paul
b89d0df535 mesa: handle numSamples=0 in _mesa_test_proxy_teximage()
Should fix the regressions reported in bug 96949.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96949
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-07-15 21:32:24 -07:00
Kenneth Graunke
aa6f60f844 nir: Use dest.ssa.num_components rather than intrin->num_components.
I recently refactored this to share code between load and atomic
lowering.  loads used intrin->num_components, while atomics used
intrin->dest.ssa.num_components.  They should be equivalent, but
Jason wanted me to use the latter.  I missed applying his review.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2016-07-15 19:42:43 -07:00
Kenneth Graunke
da3d4a4c56 nir: Update outdated intrinsic const_index comments.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-15 17:17:10 -07:00
Kenneth Graunke
52e75dcb8c nir: Use nir_intrinsic_set_base in atomic lowering.
This is more readable and also offers assertions that protect against
setting const_index fields on the wrong kind of intrinsic.

Suggested by Jason.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-15 17:17:10 -07:00
Kenneth Graunke
50b9bb9421 nir: Split nir_lower_io's input/output/atomic handling into helpers.
The original function was becoming a bit hard to read, with the details
of creating and filling out load/store/atomic atomics all in one
function.

This patch makes helpers for creating each type of intrinsic, and also
combines them with the *_op() helpers, as they're closely coupled and
not too large.

v2: Minor style nits from Jason.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-15 17:17:10 -07:00
Kenneth Graunke
e12e4af780 nir: Drop bogus nir_var_shader_in case in nir_lower_io's store_op().
This can't happen, the caller asserts that mode is shader_out or shared.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-15 17:17:09 -07:00
Kenneth Graunke
cdfc05ea6e nir: Share destination rewriting and replacement code in IO lowering.
Both loads and atomics had identical code to rewrite destinations,
and all cases had the same two lines to replace instructions.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-15 17:17:09 -07:00
Kenneth Graunke
349fe79c9b nir: Share get_io_offset handling in nir_lower_io.
The load/store/atomic cases all duplicated the get_io_offset code, with
a few tiny differences: stores didn't bother checking for per-vertex
inputs, because they can't be stored to, and atomics didn't check at
all, since shared variables aren't per-vertex.

However, it's harmless to check, and allows us to share more code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-15 17:17:09 -07:00
Kenneth Graunke
7171a9a87d nir: Make a 'var' temporary in nir_lower_io.
Less typing and word wrapping issues than intrin->variables[0]->var.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-15 17:17:09 -07:00
Kenneth Graunke
f05770121f i965: Remove the emit_linterp() helper.
Rather than computing the barycentric mode each time we emit a LINTERP,
we can simply compute it once, as soon as we know we're doing non-flat
interpolation.

At that point, emit_linterp() doesn't do much, so fold it into the
call sites and drop it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-15 17:16:54 -07:00
Kenneth Graunke
203243f5ff i965: Reduce the number of fs_reg(brw_reg) calls in LINTERP handling.
A bit tidier.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-15 17:16:54 -07:00
Kenneth Graunke
eefbbb943e i965: Make a barycentric_mode() helper function.
This combines two copies of basically the same code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-07-15 17:16:54 -07:00
Kenneth Graunke
783511e605 i965: Rename brw_wm_barycentric_interp_mode to brw_barycentric_mode.
brw_wm_barycentric_interp_mode is wordy, brw_barycentric_mode is less
typing and suffers from fewer line wrapping problems.

The enum values themselves don't really benefit from "WM" in the name,
either.  Put "BARYCENTRIC" first instead of at the end and drop "WM".

Generated by:

for file in *.c *.cpp *.h; do sed -i \
   -e 's/brw_wm_barycentric_interp_mode/brw_barycentric_mode/g' \
   -e 's/BRW_WM_\([A-Z_]*\)_BARYCENTRIC/BRW_BARYCENTRIC_\1/g' \
   -e 's/BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT/BRW_BARYCENTRIC_MODE_COUNT/g' \
   $file;
done

with a few whitespace changes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-15 17:16:54 -07:00
Kenneth Graunke
2d6dd30a9b i965: Handle default interpolation modes and locations in NIR.
This consolidates a bunch of hacks in a single place - by setting
the interpolation modes and locations on variables appropriately,
we can simply trust them in the rest of the code.  This avoids
having to handle INTERP_QUALIFIER_NONE, gl_Color overrides,
sample-shading overrides, and Gen4-5 centroid-overrides in a bunch
of places.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-15 17:16:54 -07:00
Jason Ekstrand
745f5778f3 i965/context: Remove some unnecessary vfuncs
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 16:01:43 -07:00
Jason Ekstrand
305044c5b1 i965: Get rid of gen6_surface_state.c
The only useful thing left was gen6_init_vtable_surface_functions which we
can easily put in brw_wm_surface_state.c.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 16:01:43 -07:00
Jason Ekstrand
16fb285946 i965: Use ISL for emitting buffer surface states
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 16:01:43 -07:00
Jason Ekstrand
ee229d1b9c i965/state: Account for the element size in emit_buffer_surface_state
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-07-15 16:01:43 -07:00
Jason Ekstrand
69c0dc5c53 i965/gen4-6: Use the generic ISL-based path for texture surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 16:01:43 -07:00
Jason Ekstrand
2d56959bf8 i965/gen6: Use the generic ISL-based path for renderbuffer surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 16:01:43 -07:00
Jason Ekstrand
efa7668545 i965/gen7: Use the generic ISL-based path for renderbuffer surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 16:01:43 -07:00
Jason Ekstrand
8521ce1a7e i965/gen7: Use the generic ISL-based path for texture surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 16:01:43 -07:00
Jason Ekstrand
26282a01f5 i965/gen8: Use the generic ISL-based path for renderbuffer surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 16:01:43 -07:00
Jason Ekstrand
7e951cd562 i965/gen8: Use the generic ISL-based path for texture surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 16:01:41 -07:00
Jason Ekstrand
09b5a71517 i965/state: Add generic surface update functions based on ISL
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 15:59:33 -07:00
Jason Ekstrand
1abb37baa0 i965/surface_state: Rename brw_update to gen4_update
We're about to add generic versions which work across gens and those should
have the brw name.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 15:59:33 -07:00
Jason Ekstrand
5a8c89038a i965/state: Use ISL for emitting image surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 15:59:33 -07:00
Jason Ekstrand
7a21d1bfc3 i965/blorp: Use a generic ISL path for texture surfaces on gen8
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-07-15 15:59:33 -07:00
Jason Ekstrand
5cf665afa1 i965/state: Add a helper for emitting a surface state using isl
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 15:59:24 -07:00
Jason Ekstrand
73ae4ec294 i965/blorp: Use the generic ISL path for texture surfaces on gen6
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 15:53:49 -07:00
Jason Ekstrand
cc78061003 i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen6
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 15:53:49 -07:00
Jason Ekstrand
366a6a659d i965/blorp: Use the generic ISL path for texture surfaces on gen7
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 15:53:49 -07:00