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Author SHA1 Message Date
Samuel Pitoiset
c7540d3fd6 radv: prepare for specialized DGC shaders 
The DGC prepare shader is getting crazy and it takes a non-trivial
amount of time. Using specialized DGC shaders is cleaner and it's
faster than a pile of conditional SALU instructions.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30852>
 2024-08-28 11:03:36 +00:00
David Heidelberg
0dc791ed57 freedreno: use unicode © instead of DOS-like (C) copyright sign 
Acked-by: Rob Clark <robclark@freedesktop.org>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30721>
 2024-08-28 08:54:00 +00:00
David Heidelberg
89366ff523 freedreno: Convert to SPDX-License-Identifier instead of pasting whole license 
SPDX is ISO standard now, let's leverage it to cleanup our code.

Acked-by: Rob Clark <robclark@freedesktop.org>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30721>
 2024-08-28 08:54:00 +00:00
Georg Lehmann
ef970c5a9d nir: optimize pack_uint_2x16 of pack_half(a, 0) 
Foz-DB Navi31:
Totals from 31 (0.04% of 79395) affected shaders:
Instrs: 6157 -> 6065 (-1.49%)
CodeSize: 35676 -> 34936 (-2.07%)
Latency: 23979 -> 23805 (-0.73%); split: -0.79%, +0.07%
InvThroughput: 5248 -> 5124 (-2.36%)
VALU: 3224 -> 3162 (-1.92%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30855>
 2024-08-28 07:16:55 +00:00
David Rosca
79637d5942 radeonsi/vcn: Support H264 constrained intra prediction 
We now get this flag from PPS, so it can be enabled when requested.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30842>
 2024-08-28 06:48:32 +00:00
David Rosca
c53641f810 radeonsi: Implement buf_ofst_info in si_video_resize_buffer GPU copy path 
This is used when resizing VP9 Tier1 DPB.

Fixes: 322240fcff ("radeonsi: Add GPU copy path to si_video_resize_buffer")
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30842>
 2024-08-28 06:48:32 +00:00
David Rosca
134e95cdb1 radeonsi: Enable transform_skip HEVC feature support 
This used to be hardcoded in PPS, but now it can be selected by apps.
However, we were not reporting this feature as supported in HEVC feature
flags and apps would always disable it.

Fixes: af849516f0 ("radeonsi/vcn: Use pipe header params in HEVC header encoder")
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30842>
 2024-08-28 06:48:32 +00:00
Deborah Brouwer
18f15da94d ci/intel: add i915/MTL firmware to rootfs 
Add Meteor Lake firmware directly to rootfs since it is not available
from debian package.

Signed-off-by: Deborah Brouwer <deborah.brouwer@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30770>
 2024-08-28 04:31:10 +00:00
Deborah Brouwer
0441202d6b ci: add firmware files to rootfs 
Currently only package versions of firmware files are available in the
rootfs.

This commit allows firmware files to be pulled directly from a specific
git hash of a remote repository.

Signed-off-by: Deborah Brouwer <deborah.brouwer@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30770>
 2024-08-28 04:31:10 +00:00
Caio Oliveira
695f5314d6 intel/brw: Simplify fs_inst annotation 
When INTEL_DEBUG=ann is also set, the disassembler would annotate the
output with either a string or the string verison of a NIR instruction.
This was done by keeping two pointers (but only using one at a time).

Change the code to print the instruction into a string instead of
keeping it pointer around (peg the string to the shader).  That way,
only one pointer is needed for annotations.  Because that serialization
is not free, only do that when the environment variable is set.

Since we are here, move the annotation string field to the end, moving
it to the least commonly used cacheline.  Further packing might allow
the entire fs_inst to fit in two cachelines.

For release builds, don't even add the debug annotation to the struct.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30822>
 2024-08-28 03:59:50 +00:00
Caio Oliveira
ec15cdfa2a intel/brw: Pack brw_reg struct 
The alignment required for the second union (has 64-bit size) causes
a hole between the first and second union.  Move the remaining data
there.

In 64-bit build, shrinks brw_reg from 24 bytes to 16 bytes.  And by
consequence, shirnks fs_inst from 200 bytes to 160 bytes, making it
use one less cacheline.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30822>
 2024-08-28 03:59:50 +00:00
Iván Briano
2261b298d1 anv: fix adding to wa_addr 
Fixes: 6336e0fe7f ("anv: order data in wa_bo to leave wa_addr last")

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30881>
 2024-08-27 18:10:58 -07:00
Yiwei Zhang
7941d705c3 venus: workaround cacheline overflush issue on Intel JSL 
We observed that Venus on ANV on JSL platform has some cacheline flush
issue. The overflush shows up as:
1. There're 2 threads venus bliting the feedback buffers suballocated
   from the same backing device memory, back to back.
2. On thread A, flushing the feedback buffer for cpu read is placed
   behind flushing a shader storage buffer for cpu read.
3. On thread B, flushing a different feedback buffer with the same
   backing device memory (different offset bound to) can kick the
   feedback buffer flush in (2) earlier than it should be flushed.
4. As a result, CPU polling thread for thread B results would see venus
   feedback buffer update earlier than shader storage buffer results
   being updated, breaking Venus sync primitives optimization.

During investigation, a solid workaround for JSL platform is to force
Venus to align up to 128 bytes for feedback buffer suballocation while
the default is at 64 bytes.

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30879>
 2024-08-28 00:43:59 +00:00
Eric Engestrom
c0762e88f3 ci/build: fix ppc64le and s390x jobs rules 
I think these were written with the idea of making it "(build rules) &&
(any relevant driver), but instead the driver rules are bypassing the
build rules because
1) it's not an AND, it's an OR; any line that matches applies, and
2) the driver rules are `when: on_success` when these need to be `when:
   manual` like the rest of the build jobs.

Let's stop trying to be special and simply behave like all the other
build jobs.

We can always try making complex rules later, but once we're on a base
that works.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30871>
 2024-08-28 00:11:26 +00:00
Eric Engestrom
f6eeb3c6d1 ci/image-tags: re-generate all the images building deqp-runner 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30866>
 2024-08-27 22:26:17 +00:00
Eric Engestrom
8a95129aee ci/deqp-runner: add infra to apply patches 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30866>
 2024-08-27 22:26:17 +00:00
Eric Engestrom
83d9cfa58d ci/deqp-runner: build from git checkout even on linux 
This allows things like patching deqp-runner, and unifies linux and
android.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30866>
 2024-08-27 22:26:17 +00:00
Eric Engestrom
03e50318ff ci/deqp-runner: be less verbose in the loop printing the deqp builds info 
The bash stuff printed in the middle makes it unnecessarily hard to read
the useful part of the output.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30866>
 2024-08-27 22:26:17 +00:00
Eric Engestrom
3b0c527b56 ci/deqp: simplify command to list local deqp patches 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30866>
 2024-08-27 22:26:17 +00:00
Eric Engestrom
ca7fde8761 ci/deqp-runner: restore CC after temporarily overriding it 
Fixes: 6edfb09dda ("ci/deqp-runner: unset CC for arm32 cross-compilation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30866>
 2024-08-27 22:26:17 +00:00
Sagar Ghuge
17f97a69c1 iris: Reduce clear color state alignment to 64B 
Closes https://gitlab.freedesktop.org/mesa/mesa/-/issues/10067

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26793>
 2024-08-27 21:13:30 +00:00
Sagar Ghuge
063715ed45 anv: Reduce clear color state alignment to 64B 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26793>
 2024-08-27 21:13:30 +00:00
Georg Lehmann
246e22ff4f aco/tests: do not use mul with constant to tests neg modifier 
The neg can be moved to the constant operand, which defeats the point
of the test.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30781>
 2024-08-27 20:41:10 +00:00
Georg Lehmann
bf67ac30fe aco/tests: allow literals with resolved swizzles in vop3p test 
My new optimizer code will resolve swizzles for constants.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30781>
 2024-08-27 20:41:09 +00:00
Georg Lehmann
6a18eb6afc aco/tests: parse neg(constant) in vop3p test 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30781>
 2024-08-27 20:41:09 +00:00
Georg Lehmann
52465956ca aco/print_ir: use neg() for constants 
Otherwise, it's not clear if -1 is 0xffffffff or 0x80000001.
LLVM uses a similar logic.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30781>
 2024-08-27 20:41:09 +00:00
Georg Lehmann
fb8e730d9b aco/tests: do not use add to tests neg modifer 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30781>
 2024-08-27 20:41:09 +00:00
Georg Lehmann
f71522e5cf aco/tests: don't test dpp constant propagation with row shift 
With bc=1, removing DPP for shifts is invalid.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30781>
 2024-08-27 20:41:09 +00:00
Jesse Natalie
f990322597 wgl: Add missing idep_mesautilformat 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30874>
 2024-08-27 20:16:21 +00:00
bbhtt
284ad7da39 pipe_loader_drm: Fix virtgpu_drm header path 
Fixes: 2ea4a59ab7 ("loader: Add better
support for virtgpu nctx driver loading")

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30673>
 2024-08-27 19:36:24 +00:00
Eric Engestrom
25ba90fd88 vc4/meson: simplify neon build now that the android build system doesn't exist anymore 
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30854>
 2024-08-27 18:32:01 +00:00
Mike Blumenkrantz
9777f016c7 egl/x11: pretend kopper is software with LIBGL_KOPPER_DRI2 
there's no render device fd here, so take the sw path on startup

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30872>
 2024-08-27 17:41:37 +00:00
Mike Blumenkrantz
aae62e5d29 egl: unify LIBGL_KOPPER_DRI2 checks 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30872>
 2024-08-27 17:41:37 +00:00
Konrad Dybcio
d94d152498 freedreno: Add initial A621 support 
Baby A650 found in some peculiar SoCs

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30253>
 2024-08-27 17:06:55 +00:00
Karol Herbst
b77eca8a95 vtn: mark ImageMipmap as supported 
The SPIRV-LLVM-Translator seems to also set that cap for MSAA cl images,
but it looks like it works just fine in regards to LODs as well.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30834>
 2024-08-27 15:06:17 +00:00
Karol Herbst
fc88f04ba1 vtn, nir: handle OpImageQueryLevels on images 
This is needed for cl_khr_mipmap_image, specifically the OpenCL C
function get_image_num_mip_levels.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30834>
 2024-08-27 15:06:17 +00:00
Karol Herbst
260a50add5 nir: Support multisampled images in lower_read_only_images_to_tex() 
This is needed for cl_khr_gl_msaa_sharing

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30834>
 2024-08-27 15:06:16 +00:00
Karol Herbst
c5e38d5cb8 compiler/types: Add multisample vimage/vtexture types 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30834>
 2024-08-27 15:06:16 +00:00
Karol Herbst
9982568fa8 clc: add support for more image related extensions 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30834>
 2024-08-27 15:06:16 +00:00
Samuel Pitoiset
2fda0db66f ac,radeonsi,radv: add common GFX preambles 
RADV and RadeonSI have a few differences.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30789>
 2024-08-27 14:14:57 +00:00
Samuel Pitoiset
80e8e18cc6 ac: add ac_gfx103_get_cu_mask_ps() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30789>
 2024-08-27 14:14:57 +00:00
Lionel Landwerlin
e97b968aeb brw: add a comment what Gfx12.5 URB fences 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30849>
 2024-08-27 13:38:14 +00:00
Lionel Landwerlin
93fba40389 brw: switch mesh/task URB fence prior to EOT to GPU 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30849>
 2024-08-27 13:38:14 +00:00
Eric Engestrom
fda6f8638a vc4: Add missing libvc4_neon build dependencies 
Duplicates the libvc4 dependencies.

Fixes: ebcb4c2156 ("meson: Enable VC4's NEON assembly support.")
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Co-authored-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30819>
 2024-08-27 13:10:28 +00:00
Samuel Pitoiset
9bfb23b252 radv: rework computing the DGC cmdbuf layout 
This is much better and less error prone because the offset/size are
computed in only one place now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30868>
 2024-08-27 12:36:36 +00:00
Sergi Blanch Torne
156c1b0547 New testing jobs zink-anv-adl{,-full} 
Introduce testing coverage for Zink in ANV driver in ADL generation. One job
in the pre-merge fraction, and 2 for the full coverage on the nightly runs.
Introduced the initial expectation files with fails, flakes, and skips.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26831>
 2024-08-27 12:49:31 +02:00
Sergi Blanch Torne
1b51e24b0a New testing jobs intel-adl-skqp 
Introduce skqp testing on ADL generation. Only one job on the pre-merge, and
no fraction needed, so not required to set up a job for nightly runs.
Introduced the initial expectation files with fails, flakes, and skips.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26831>
 2024-08-27 12:49:28 +02:00
Sergi Blanch Torne
c653e98748 New testing jobs anv-adl-angle{,-full} 
Introduce testing coverage for Angle in ANV driver on ADL generation. One job
in the pre-merge fraction, and another for the full coverage on the nightly
runs. Introduced the initial expectation files with fails, flakes, and skips.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26831>
 2024-08-27 12:49:24 +02:00
Sergi Blanch Torne
6c9138f86a New testing jobs anv-adl{,-full} 
Introduce testing coverage for ANV driver on ADL generation. Sharded in 4 jobs
the pre-merge fraction, and with 5 jobs the full coverage on the nightly runs.
Introduced the initial expectation files with fails, flakes, and skips.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26831>
 2024-08-27 12:49:21 +02:00
Sergi Blanch Torne
fce5e77604 New DUT for Alder Lake 
Introduce a new runner tag from a hidden job for ADL (Alder Lake Intel
generation), known as brya.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26831>
 2024-08-27 12:49:16 +02:00