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715 Commits

Author SHA1 Message Date
Rohan Garg
c69650a95e isl,blorp,anv: introduce ISL_TILING_64_XE2 for Xe2+ platforms 
Xe2+ changed the msaa mapping for 2D/3D Tile64 surfaces, introduce a
Xe2+ specific enum to handle this change.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27113>
 2024-01-24 17:01:48 +01:00
Lionel Landwerlin
0bc6462924 isl: add print helpers for debug 
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27169>
 2024-01-23 08:03:12 +00:00
José Roberto de Souza
475661a64e intel/isl/xe2: Disable route of Sampler LD message to LSC 
This optimization is causing some tests groups to fail, like:
dEQP-VK.image.mutable.2d_array.*
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.*

So disabling it until properly fixed.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27016>
 2024-01-12 01:51:59 +00:00
Lionel Landwerlin
f12ffc6b04 isl: implement Wa_22015614752 
This workaround requires 64Kb alignment for compression with multiple
engine accesses.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8614
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26890>
 2024-01-08 08:21:14 +00:00
Lionel Landwerlin
32450d0901 isl: further restrict alignment constraints 
We can limit the AUX-TT requirements to formats supporting CCS.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26890>
 2024-01-08 08:21:14 +00:00
Mark Janes
590fe58ef6 intel: remove MTL a0 workarounds 
Meteorlake shipped with the b0 stepping.  Remove fixes for hardware
bugs that were corrected prior to the platform release.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26898>
 2024-01-05 22:51:46 +00:00
Tapani Pälli
fe5c82e853 isl: implement Wa_14018471104 
Set EnableSamplerRouteToLSC in case ResourceMinLOD is 0.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
 2024-01-02 21:14:42 +00:00
José Roberto de Souza
70382f7f06 intel/isl/xe2: Enable route of Sampler LD message to LSC 
Xe2 allows route of LD messages from Sampler to LSC to improve
performance when some restrictions are met.

BSpec: 57023
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
 2024-01-02 21:14:42 +00:00
Zhang, Jianxun
e9b633619c intel/genxml: Add RENDER_SURFACE_STATE for xe2 
The indirect BO of clear color is also removed along with clear value
address and its enabling.

Other delta in struct RENDER_SURFACE_STATE are deferred to their
functional enabling changes.

Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
 2024-01-02 21:14:42 +00:00
Nanley Chery
94e5b5d049 isl: Handle MOD_INVALID in clear color plane check 
In iris, if whandle->modifier is DRM_FORMAT_MOD_INVALID within
iris_resource_from_handle, isl_drm_modifier_plane_is_clear_color will
assert fail on non-existent modifier info. Update that function to
return early instead.

Fixes the assert failure when running the piglit test case:

   ext_image_dma_buf_import-sample_yuv -fmt=YVYU -auto

   ext_image_dma_buf_import-sample_yuv: ../../src/intel/isl/isl.h:2352:
      isl_drm_modifier_plane_is_clear_color: Assertion `mod_info' failed.

Fixes: 81d132d5ea ("iris: Use helpers for generic aux plane importing")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26826>
 2023-12-29 09:08:57 +00:00
Jianxun Zhang
1b8a07095d intel/isl: Add Gfx 12.x RC_CCS_CC into modifier scores 
Add RC_CCS_CC drm modifiers of TGL, DG2 and MTL into
the list with a higher score than RC_CCS modifiers.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Jianxun Zhang
f280b6e8d5 intel: Move mod_plane_is_clear_color() into isl 
We are going to reuse this helper in anv driver and
also rename it.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Jianxun Zhang
3b885926e9 intel/isl: Add a debug option to override modifer list 
Developers can limit supported modifers to a single
modifier provided in INTEL_MODIFIER_OVERRIDE environment
variable for debug purposes. For example, setting it
makes Vulkan CTS only run modifier tests against the
specified modifier instead of all modifiers in production
code.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25651>
 2023-12-19 13:57:16 +00:00
Zhang, Jianxun
80d9294d2d intel/isl: update 3DSTATE_STENCIL_BUFFER (xe2) 
Update xml file and adjust driver code to compile.

Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Rohan Garg
9512f61cd8 iris,isl: Adjust driver for several commands of clear color (xe2) 
The xe2 xml will be updated in following commits. Commit message
has been updated by Jianxun.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600>
 2023-12-18 15:41:30 +00:00
Lionel Landwerlin
d761871761 isl: drop AUX-TT CCS alignment with INTEL_DEBUG=noccs 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26644>
 2023-12-13 17:40:38 +00:00
Lionel Landwerlin
a1dcf943ab isl: constify isl_device_get_sample_counts() 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26632>
 2023-12-13 09:39:08 +00:00
Jordan Justen
7be8bc2c97 isl: Add mocs for xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26593>
 2023-12-12 17:54:38 +00:00
Yonggang Luo
36480b4d02 intel: Generate source file with utf-8 encoding from mako template 
Make them generated in consistent way

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26515>
 2023-12-07 12:41:07 +00:00
José Roberto de Souza
969af605fe intel/isl: Set mocs.blitter_dst/src for MTL 
This fields are required to be set because those are used by
XY_FAST_COLOR_BLT instruction.
Right now it is not set causing applications to abort because
DestinationMOCS is required to be non-zero.

This fixes at least piglit@ext_external_objects-vk-image-display on MTL.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26502>
 2023-12-06 20:09:04 +00:00
Lionel Landwerlin
d4499c4cb2 isl: disable MCS compression on R9G9B9E5 
Not supported according to the docs and will trigger an assert
isl_get_render_compression_format().

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26112>
 2023-11-09 20:20:43 +00:00
Sagar Ghuge
2a9f8a256a isl: Enable MCS compression on ACM platform 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26043>
 2023-11-07 23:00:18 +00:00
Jani Nikula
ae74d486ad docs/isl: use hawkmoth instead of doxygen 
Use the hawkmoth c:auto* directives to incorporate isl documentation.

Convert @param style parameter descriptions to rst info field lists.
Add static stubs for generated headers. Fix a lot of references, in
particular the symbols are now in the Sphinx C domain, not C++
domain. Tweak syntax here and there.

Based on the earlier work by Erik Faye-Lund <kusmabite@gmail.com>

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24507>
 2023-10-26 16:13:26 +00:00
Jani Nikula
0ed5b8af01 isl: drop **< style documentation comments 
Prepare for using Hawkmoth.

Hawkmoth does not support trailing comments using /**< ... */
syntax. Replace with regular documentation comments.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24507>
 2023-10-26 16:13:25 +00:00
Nanley Chery
d57611fe25 intel/isl: Add scores for GEN12_RC_CCS and MTL_RC_CCS 
Now that these CCS-enabled modifiers have non-zero scores, anv is
enabled to use them.

We found this to improve the performance of Borderlands 3 by 18.73%.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6701
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Tested-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25003>
 2023-10-23 21:37:24 +00:00
Sagar Ghuge
9d7166dfc0 isl: Use 16-bit instead of 8-bits for surface format info fields 
Comparing uint8_t max value 255 with devinfo->verx10 will work fine for
now but for future platforms, comparison will fail. To avoid this
let's switch the field data type from 8-bits to 16-bits.

v1: (Jordan)
- Use 16 bits instead of 32 and add assertion.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25478>
 2023-10-02 17:24:33 +00:00
Paulo Zanoni
e4598f0eea intel/isl: simplify the check for maximum surface size 
The only thing that changes between these 3 checks is the size.

This entire patch was suggested by Kenneth Graunke, I just converted
his gitlab comment to a git commit.

Credits-to: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
 2023-09-28 06:16:40 +00:00
Paulo Zanoni
0de5d142e8 intel/isl: add ISL_SURF_USAGE_SPARSE_BIT 
Vulkan Sparse resources have their own set of rules, so here we try to
make ISL aware of them through ISL_SURF_USAGE_SPARSE_BIT.

The big deal here is when some image ends up not using Tile64 nor
TileYs. Previously Ys was not supported on TGL at all, and Tile64 did
not have support for 3D. Now we still have some formats that end up
not being used with either Tile64 and Ys, but need to support Sparse
on them (e.g., YUV on Tile64). In the future we may have new tiling
formats or hardware restrictions that would force this case to happen
again.

So here we do some adjustments so we can make sparse work with other
tiling formats, although with limited functionality (e.g., those
formats may be restricted to opaque binds, and certainly don't support
the standard block shapes).

v2: before we had Ys support, we had defined TGL's block size as 4k.
v3: move the size_B chunk to before nte notify_failure() checks (Ken).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23045>
 2023-09-28 06:16:40 +00:00
Jordan Justen
08735fd90d intel/isl: Build for Xe2 
This is only *build* support in isl for Xe2. Before adding LNL PCI
IDs, subsequent patches will fill in ISL updates for Xe2.

Rework:
 * Rohan: Update isl_genX_declare_get_func

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25253>
 2023-09-21 18:24:01 +00:00
Lionel Landwerlin
8a32614a18 isl/tilememcpy_test: add multiple tile testing 
Also verify that there is no out-of-bounds accesses.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Aditya Swarup <aditya.swarup@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
 2023-09-02 21:49:05 -07:00
Aditya Swarup
a6c8ddb596 intel/isl: Linear to Tile-4 conversion unittest 
Add unittest to test conversion of data from linear to
Tile-4 format based on bit swizzling conversion info
mentioned in Bspec.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
 2023-09-02 21:49:05 -07:00
Aditya Swarup
4f0d02902e intel/isl: Convert Tile4 texture to linear format 
Add memcpy function to convert Tile-4 4KB texture to linear
format.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
 2023-09-02 21:49:05 -07:00
Aditya Swarup
a648ee7a70 intel/isl: Convert linear texture to Tile4 format 
Add memcpy function to convert linear data to Tile 4 format.
Tile 4 format consists of 4KB block divided into chunks of 512B.
Each 512B chunk/block is comprised of 8 64B blocks arranged in
Y-tile format.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
 2023-09-02 21:49:05 -07:00
Aditya Swarup
d16eac17d8 intel/isl: Unittest for linear to Ytile conversion 
Add unittests for linear to tiled and tiled to linear texture
conversions for Ytile. The test prints the source/output buffer
in hex format with debug flags to verify the result.

Linear to tile conversion fills the linear buffer with values
based on the OWORD index number i.e., OWORD3 will contain
all values filled as 0x03 and
OWORD3 = 0x03030303030303030303030303030303.

The Y-tile to Linear tile conversion uses a similar logic to place
the tiled values in a manner that will result in a linear buffer with
OWORDs filled according to index number as mentioned above.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
 2023-09-02 21:49:03 -07:00
Aditya Swarup
e03f3b646c isl: enable Tile64 for 3D images 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Jason Ekstrand
e956f6ad30 intel/isl: Allow Ys tiling 
Ys & Yf are both implemented in ISL now, we still have some Yf issues
to investigate. Instead of disabling them in ISL, we disable them in
the two drivers.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Lionel Landwerlin
4ac46dbb46 isl: reorder tiling selection 
Select tilings in this order :
  - recommended Y tilings
  - Yf tilings
  - Ys/Tile64 tilings
  - legacy tilings (W, X) & Linear

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Lionel Landwerlin
e182f5770d isl: disable CCS on Ys/Yf 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Lionel Landwerlin
4e36aa507e isl: disable miptails on gfx12 with yuv formats 
A number of CTS tests are failing, like :

   dEQP-VK.ycbcr.format.b8g8r8g8_422_unorm.vertex_optimal

Failures are reproduced on simulation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Lionel Landwerlin
aa31683dde isl: disallow miptails on planar formats 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Lionel Landwerlin
7ee41c162d isl: add Gfx12/12.5 restriction on 3D surfaces & compression 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Jason Ekstrand
63c86a95b2 intel/isl: Disallow CCS on 3D surfaces with miptails 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Jason Ekstrand
46f45d62d1 intel/isl: Start using miptails 
This commit adds the code for choosing where to start the miptail and
enables miptails by default unless the client driver passes
info->min_miptail_start_level >= info->levels.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Jason Ekstrand
a42d808b71 intel/isl: Support miptails in isl_surf_get_uncompressed_surf 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Lionel Landwerlin
866af3d8fa isl: make isl_surf_get_uncompressed_surf robust to argument accesses 
Since the input & output arguments can point to the same location in
memory, if you ever access the input after writing the output you're
in trouble.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:18 +00:00
Jason Ekstrand
988fa2006a intel/isl: Add support for computing offsets with miptails 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Lionel Landwerlin
1ada5f5490 intel/isl: Add a max_miptail_levels field to isl_tile_info 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand
b1862a0964 intel/isl: Add initial data-structure support for miptails 
This commit just adds a miptail start field to isl_surf and wires it up
in the RENDER_SURFACE_STATE and 3DSTATE_DEPTH code.  We also add a
minimum miptail LOD so that client drivers have a knob to control the
miptails a bit.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand
68ac5c2165 intel/isl: Support Yf/Ys tiling in emit_depth_stencil_hiz 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00
Jason Ekstrand
01b50c9dac intel/isl: Support Yf/Ys tiling in surf_fill_state 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
 2023-09-01 23:22:17 +00:00