Commit Graph

168302 Commits

Author SHA1 Message Date
Alyssa Rosenzweig
c4aa7828b3 asahi: Use a dynarray for writers
We don't want a writer hash table with persistent pointers to resources, because
the resources could be freed without the hash table being updated (even though
the underlying BO will not be freed until it's ready). To avoid the reference
count hell, do away with the pointer hash table and instead use a flat dynarray
for mapping BO (handles) to writer (batch indices).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21620>
2023-03-16 20:42:01 +00:00
Tatsuyuki Ishi
0cde42a506 radv: Wait for shader uploads asynchronously.
This introduces tracking of the required semaphore values in pipelines,
which is then propagated to cmd_buffers on bind. Each queue also keeps
track the maximum count it has waited for, so that we can avoid the waiting
overhead once all the shaders are loaded and referenced.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16271>
2023-03-16 18:02:57 +00:00
Tatsuyuki Ishi
a8c5fd3b1b radv: Upload shaders to invisible VRAM on small BAR systems.
Following PAL's implementation, this patch avoids allocating shader code
buffers in BAR and use SDMA to upload them to invisible VRAM
directly.

For some games like HZD, shaders can take as much as 400MB, which exceeds
the non-resizable BAR size (256MB) and cause inconsistent spilling
behavior. The kernel will normally move these to invisible VRAM on its own,
but there are a few cases that it does not reliably happen. This patch does
the moving explicitly in the driver to ensure predictable results.

In this patch, we upload the shaders synchronously; so the shader will be
ready as soon as vkCreate*Pipeline returns. A following patch will make
this asynchronous and don't block until we see a use of the pipeline.

As a side effect, when SQTT is used we now store the shaders on a cacheable
buffer which would speed up writing the trace to the disk.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16271>
2023-03-16 18:02:57 +00:00
Tatsuyuki Ishi
3b258ae2d9 radv: Introduce sdma_copy_buffer for GFX7+.
Helper salvaged from radeonsi (before SDMA removal).

This will be used for driver internal submissions to DMA shaders from GTT
to invisible VRAM.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16271>
2023-03-16 18:02:56 +00:00
Tatsuyuki Ishi
d4fb3db748 radv: Use radeon_cmdbuf for sdma_copy_image.
For consistency with the sdma_copy_buffer helper that will be added next.

As a general justification, SDMA commands require little state tracking and
using radeon_cmdbuf makes it more suitable for driver internal use.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16271>
2023-03-16 18:02:56 +00:00
Jesse Natalie
25b1a11401 Revert "CI: Disable Windows runners"
This reverts commit 023d7e860e.

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21932>
2023-03-16 16:07:14 +00:00
Jesse Natalie
f8566533ea radv: Fix returning an expression from a void function
Fixes: d5de56bf ("radv: add RT shader args")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21932>
2023-03-16 16:07:14 +00:00
Jesse Natalie
5c4c9fd454 vulkan/wsi: Fix Windows build
The headless path doesn't build for Windows (yet, anyway).

Fixes: d4a2c0fc ("vulkan/wsi: add a headless swapchain implementation/option")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21932>
2023-03-16 16:07:14 +00:00
Anuj Phogat
a455f80395 iris: implement TES distribution mode WA 22012785325
Set TEDMODE_RR_STRICT when TEEnable is set.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21899>
2023-03-16 14:42:53 +00:00
Anuj Phogat
b4b43aa912 anv: implement TES distribution mode WA 22012785325
Set TEDMODE_RR_STRICT when TEEnable is set.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21899>
2023-03-16 14:42:53 +00:00
Eric Engestrom
cb7e9a6cfb asahi: replace copies of .clang-format with symlinks
Avoid all the issues of having to keep them in sync, and few-enough
people (read: probably no-one ever) will be working on the asahi driver
from a Windows machine, so symlinks can be relied upon, especially for
something optional like automatic code formatting.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21951>
2023-03-16 14:28:20 +00:00
Tatsuyuki Ishi
9faaff4561 radv/rt: Don't upload the prolog twice.
radv_shader_create already calls radv_shader_binary_upload.

Fixes: 4b92a53285 ("radv: add radv_create_rt_prolog()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21945>
2023-03-16 12:27:21 +00:00
Eric Engestrom
8f6126e21a v3dv/ci: fix test name (,Fail is not part of the test name)
Fixes: a0bf0adade ("ci/broadcom: move rare failure to the flakes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21954>
2023-03-16 12:03:14 +00:00
Martin Roukala (né Peres)
77c3df53ae zink/ci: update the radv expectations
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21873>
2023-03-16 11:31:04 +00:00
Martin Roukala (né Peres)
c69e2849a6 zink/ci: increase the parallelism of zink-radv-vangogh-valve
It current takes 17 minutes to run this job, which is above the 15
minutes target for Mesa CI. Let's increase the parallelism to reduce
exec time to closer to 13 minutes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21873>
2023-03-16 11:31:04 +00:00
Martin Roukala (né Peres)
928aab57a3 radv/ci: reduce the parallelism for vkcts-vangogh
We are about to enable pre-merge testing for radv-zink on vangogh,
which would mean the steam decks would be used for the following jobs:

 * Mesa pre-merge CI:
  * zink: 3 (~12 minutes)
 * Mesa Post-merge CI:
   * vkcts: 4 (~30 minutes)
   * vkd3d: 1 (~5 minutes)
 * DXVK CI: 1 (takes ~4 hours)

This means we could have 9 jobs running at the same time on steam
decks, despite only having 6 available. By reducing the number of decks
allocated for VKCTS runs from 4 to 2, we get closer to the actual
availability, and since vkd3d is so short + DXVK CI runs so
infrequently, we should never have to wait for a deck for too long!

Unfortunately, with the change of parallelism, a known flake started
failing more consistently, so I added it to the flakes list.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21873>
2023-03-16 11:31:03 +00:00
Erik Faye-Lund
5c5c114fa2 meson: correct typo in comment
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21868>
2023-03-16 10:31:04 +00:00
Gert Wollny
3ddbf64e41 virgl: Lower binding start into buffer indices
This requires that we limit the number of max combinded SSBOs to 31,
otherwisewe shaders that use SSBO binding points with higher values
will break on the host.

Fixes CTS:
  KHR-GL43.shader_storage_buffer_object.basic-atomic-case1
  KHR-GL43.shader_storage_buffer_object.basic-atomic-case2
  KHR-GL43.shader_storage_buffer_object.advanced-indirectAddressing-case2
  KHR-GL43.shader_storage_buffer_object.advanced-usage-case1
  KHR-GL43.shader_storage_buffer_object.advanced-usage-sync
  KHR-GL43.shader_storage_buffer_object.advanced-matrix

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>
2023-03-16 09:30:00 +00:00
Gert Wollny
99416624e5 ntt: add option to lower SSBO bindings to buffer index
When a shader uses SSBOs in various shader stages, then we have to track
the binding locations in order to be able to properly bind these SSBOs.

Therefore add a flag that enables adding the start index of the bindings to
the SSBO index.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>
2023-03-16 09:30:00 +00:00
Gert Wollny
1247b23f28 virgl: Don't try to do re-alloc or readback by transfer for blob resources
Blob resources are mapped directly, no need to copy data around, and
in any case, neither the resource nor the transfer info will have an
IOV attached to it, so the transfer would result error out on the host
anyway.

In addition, blob resources should not use re-allocation.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>
2023-03-16 09:30:00 +00:00
Gert Wollny
831e7818aa virgl: Enable AMD_vertex_shader_(layer|viewport_index) when host supports it
This increase the number of cases when the texture upload from buffer
can use the PBO upload code path.

v2: Fix logic combination (Corentin)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21586>
2023-03-16 09:30:00 +00:00
Constantine Shablya
d53aba56db anv: use vk_get_physical_device_features
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>
2023-03-16 08:23:29 +00:00
Alyssa Rosenzweig
ded810ded5 panvk: Use vk_get_physical_device_features
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>
2023-03-16 08:23:28 +00:00
Constantine Shablya
723825f5c7 vulkan: use vk_features for vk_device::enabled_features
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>
2023-03-16 08:23:28 +00:00
Constantine Shablya
c7300a6a3b vulkan: add hepler for vkGetPhysicalDeviceFeatures2
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>
2023-03-16 08:23:28 +00:00
Constantine Shablya
efaf3fd5fc vulkan: delete trailing namespace
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>
2023-03-16 08:23:28 +00:00
Constantine Shablya
cd35ab9570 vulkan: tidy up vk_physical_device_features
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>
2023-03-16 08:23:28 +00:00
Constantine Shablya
b0b3b9e8b1 vulkan: relocate rmv to its correct home
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21754>
2023-03-16 08:23:28 +00:00
Qiang Yu
51e725df29 radeonsi: monolithic TCS emit tessfactor in nir directly
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:31 +00:00
Qiang Yu
3f5d42a28a radeonsi: lower nir_load_ring_tess_factors_offset_amd
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:30 +00:00
Qiang Yu
719366c2b2 ac/llvm,radeonsi: lower nir_load_ring_tess_factors_amd
No one implement this intrinsic in llvm, so remove the
llvm entry too.

This will be used in TCS nir tess factor write.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:30 +00:00
Qiang Yu
99828e0390 ac/nir: handle tess factor output missing case
tcs_tess_lvl_(in|out)_loc may be not set if user miss tess
factor output.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:30 +00:00
Qiang Yu
700e24941c ac/nir: init tess factor location with IO remap
Radeonsi is going to use nir tess factor write, so need to
remap tess factor location.

RADV set tess factor driver location to be 0 and 1 in
get_linked_variable_location(). While radeonsi also set them
to be 0 and 1 in st->map_io aka. si_shader_io_get_unique_index_patch().

We could just set them to be 0 and 1 at the beginning of
ac_nir_lower_hs_outputs_to_mem(), but in order to keep the
location map at the same place, we still do this in
lower_hs_output_store().

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:30 +00:00
Qiang Yu
c06329eb3f ac/nir: tcs write tess factor support pass by reg
For radeonsi usage.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:30 +00:00
Qiang Yu
e070a9e8d0 ac/nir: move store_var_components to common place
It will be shared by other nir lowering too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21437>
2023-03-16 04:33:30 +00:00
Alyssa Rosenzweig
f2617944bf panfrost: Don't round up Midgard polygon list BOs
Rounding up the polygon list BO can waste large amounts of memory. In a common
case I observed, it rounded up 11MB to 16MB, wasting 5MB. That adds up quickly
across processes, especially on the 2GB machines.

This only applies to Midgard. On Bifrost and newer, the driver does not
explicitly allocate this data structure. Cc stable because this rounding is
incorrect and the increase in RAM usage can cause real problems (especially
given how slow the shrinker is).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21831>
2023-03-16 04:13:46 +00:00
Timothy Arceri
174d6e6a54 glsl: allow 64-bit integer on RHS of shift
Fixes: 9ba9a7f854 ("glsl: Add 64-bit integer support to some operations.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6862

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21919>
2023-03-16 02:26:30 +00:00
Daniel Schürmann
39c828cb9f aco: remove aco::rt_stack variable
Since we initialize scratch in the RT proglog,
there is no need for this variable anymore.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
f123d65e9f radv/rt: use prolog for raytracing shaders
Co-authored-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Friedrich Vock
bea022d1f6 radv/rt: Add shader config combination/postprocessing utils
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Friedrich Vock
0569b350ed radv: Emit RT shader VA user SGPR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
a16df842a6 radv: compile rt_prolog
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
4b92a53285 radv: add radv_create_rt_prolog()
Co-authored-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
6446b79168 aco: implement select_rt_prolog()
Co-authored-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
7d35bf24f6 aco: create hw_init_scratch() function for p_init_scratch lowering
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
2fee99a36c aco: implement load_ray_launch_{id|size}
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
c7c68e1193 aco: move rt_dynamic_callable_stack_base_amd to VGPR
In future, we will use a VGPR arg for that between RT stages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
1f01a86b36 aco: don't set private_segment_buffer/scratch_offset on GFX9+
It is unused. Also don't initialize scratch in raytracing stages as it gets
initialized in the prolog shader.

Co-authored-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:30 +00:00
Daniel Schürmann
a33b9d43d8 aco: add RT stage enums
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:29 +00:00
Daniel Schürmann
c38b8678c9 radv: add RT shader handling to radv_postprocess_config
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21780>
2023-03-16 01:40:29 +00:00