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Author SHA1 Message Date
Rhys Perry
79c8740c6e aco: fix fp16 opcode definitions 
The v_fma_mix optimizations assume v_cvt_f16_f32 and v_mul_f16 use a v2b
definition.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14769>
 2022-03-17 19:04:17 +00:00
Dylan Baker
6d4eb4a72e mesa/main: replace use of simple_list with util/list 
Because really, do we want simple_list?

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14983>
 2022-03-17 18:25:55 +00:00
Dylan Baker
4b10a4aaaa util/list.h: Add docstrings for list_add and list_addtail 
Which have easily confused parameters: the first argument is the item to
be added, the second is the list to add to; but this could easily be the
other way around.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14983>
 2022-03-17 18:25:55 +00:00
Alyssa Rosenzweig
b0faf422b7 pan/va: Use XML for special FAU page 0 
Now all special FAU handling is unified, which makes both assembler and
disassembler considerably nicer. This adds some more special FAU indices from
page 0 that were previously missing, allowing them to be assembled and
disasembled.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364>
 2022-03-17 18:06:17 +00:00
Alyssa Rosenzweig
31a171d92d pan/va: Use boring names for FAU special pages 1/3 
There's no magic underlying interpretation, be.. uniform.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364>
 2022-03-17 18:06:17 +00:00
Alyssa Rosenzweig
76159ee379 pan/va: Remove immediate modes from XML/asm 
Now replaced by inference in the assembler, as they should be.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364>
 2022-03-17 18:06:17 +00:00
Alyssa Rosenzweig
81498f1538 pan/va: Use 64-bit special FAU for pages 1 and 3 
This aligns with how the hardware actually sees special FAU.

Also fix the names while we're at it.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364>
 2022-03-17 18:06:17 +00:00
Alyssa Rosenzweig
139867cb43 pan/va: Rename imm_mode -> fau_page 
In accordance with new information on the hardware.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364>
 2022-03-17 18:06:17 +00:00
Alyssa Rosenzweig
3bd1401075 pan/va: Handle uniforms from page 1 
Like Bifrost, Valhall can access 2x as many fast acess uniforms as previously
thought. However, on Valhall this requires using the pagination mechanism.
Support this in the dis/assembler.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364>
 2022-03-17 18:06:17 +00:00
Alyssa Rosenzweig
cf43a1cc58 pan/va: Rewrite FAU handling in dis/assembler 
FAU pages do not need to be specified explicitly in the assembly. Rather, they
should be inferred by the assembler by the instructions used. Rewrite the code
handling this in alignment with new information about the hardware.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364>
 2022-03-17 18:06:17 +00:00
Alyssa Rosenzweig
95b7908d2d pan/va: Fix BLEND instruction 
There's only one staging register, the other register is just offset due to the
Msg64 source.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364>
 2022-03-17 18:06:17 +00:00
Alyssa Rosenzweig
c7e8e8b319 pan/va: Handle 64-bit sources in message instrs 
These take up two slots, reading an aligned register pair, even though they are
in a 32-bit instruction. Required to correctly model BLEND.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364>
 2022-03-17 18:06:17 +00:00
Alyssa Rosenzweig
9878469833 pan/va: Add start property to source 
The bit position of sources is more complicated than (8 * index). Make it a part
of the Valhall reflection information.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364>
 2022-03-17 18:06:17 +00:00
Alyssa Rosenzweig
5a759140b0 pan/va: Fix typo in BLEND text 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364>
 2022-03-17 18:06:17 +00:00
Tomeu Vizoso
96e17287b4 ci/freedreno: Disable a618 jobs 
Some of these machines are experiencing networking problems currently.
Disable for now so people aren't blocked.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15430>
 2022-03-17 17:43:06 +00:00
Erik Faye-Lund
115298b71e gallium: rename ballot cap 
This cap is no longer TGSI specific, so let's rename it to reflect
reality.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316>
 2022-03-17 16:44:42 +00:00
Erik Faye-Lund
b3ce733da9 gallium: rename clock cap 
This cap is no longer TGSI specific, so let's rename it to reflect
reality.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316>
 2022-03-17 16:44:42 +00:00
Erik Faye-Lund
7984c5884c gallium: rename group-vote cap 
This cap is no longer TGSI specific, so let's rename it to reflect
reality.

Because the name got a bit vague when removing the TGSI-bits, let's add
some more details to the name.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316>
 2022-03-17 16:44:42 +00:00
Erik Faye-Lund
a6d7ead686 gallium: rename texture query samples cap 
This isn't specific to TGSI, so let's update the name to reflect
reality.

Because the name of the opcode was TGSI specific, let's pick a new one,
based on the naming of the PIPE_CAP_TEXTURE_QUERY_LOD cap.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316>
 2022-03-17 16:44:42 +00:00
Erik Faye-Lund
930b38e7cd gallium: rename read-outputs cap 
This cap is no longer TGSI-specific, so let's update the name to reflect
reality.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316>
 2022-03-17 16:44:42 +00:00
Erik Faye-Lund
2dff9bea4f gallium: rename array-components cap 
This cap is no longer TGSI specific, so let's update the name to reflect
reality.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316>
 2022-03-17 16:44:42 +00:00
Erik Faye-Lund
350329feb1 gallium: rename sysval caps 
These aren't spiecic to TGSI any more, so let's rename them to reflect
reality.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316>
 2022-03-17 16:44:42 +00:00
Erik Faye-Lund
df40de91d9 gallium: rename fine derivative cap 
This is no longer TGSI specific, so let's rename it to reflect the
reality.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316>
 2022-03-17 16:44:42 +00:00
Erik Faye-Lund
2a8e11e101 gallium: rename pixel-coord caps 
These aren't specific to TGSI, so let's rename them to reflect the
reality.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316>
 2022-03-17 16:44:42 +00:00
Erik Faye-Lund
89797fac56 gallium: rename layer-viewport caps 
Similar to the previous commits, these aren't TGSI specific, so let's
drop TGSI from their name.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316>
 2022-03-17 16:44:41 +00:00
Erik Faye-Lund
8ac7dc9cf6 gallium: rename vs instance id cap 
This cap is no longer specific to TGSI, so let's rename it and update
the documentation to reflect that.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316>
 2022-03-17 16:44:41 +00:00
Erik Faye-Lund
f8809fbdb8 gallium: rename pack half-float cap 
This cap no longer has anything to do with TGSI, as the lowering happens
on GLSL IR, and applies just as much to NIR drivers. So let's rename
this cap and update the docs to reflect the current situation.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15316>
 2022-03-17 16:44:41 +00:00
Jason Ekstrand
0f048c5782 panvk: Convert to the common sync/submit framework 
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15296>
 2022-03-17 16:22:10 +00:00
Lionel Landwerlin
d68b9f0e6b anv: zero-out anv_batch_bo 
anv_batch_bo has a length field that we use to flush cachelines. Not
having that field initialized properly leads us to access out of bound
memory.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15425>
 2022-03-17 15:56:14 +00:00
Lionel Landwerlin
78acae3865 anv: fix variable shadowing 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 83fee30e85 ("anv: allow multiple command buffers in anv_queue_submit")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15425>
 2022-03-17 15:56:14 +00:00
Samuel Pitoiset
174d086e8c radv: enable radv_disable_aniso_single_level for DXVK/vkd3d 
It seems the default D3D behavior and it's complicated to emulate this
in DXVK/vkd3d. Enable it by default to prevent rendering issues in
other games not listed here.

Cc: 22.0 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15368>
 2022-03-17 15:10:06 +00:00
Samuel Pitoiset
590eb9d640 radv: do not compute the cache UUID for LLVM if it's not used 
If the LLVM version (even minor) isn't the same on the OS that
precompiles shaders vs the OS that runs them, the cache UUID would
be different, even if only ACO is used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15406>
 2022-03-17 14:49:35 +00:00
Sagar Ghuge
2e336c602d intel/fs: Add Wa_14014435656 
For any fence greater than local scope, always set flush type to at
least invalidate so that fence goes on properly.

v2: Fixup condition to trigger workaround (Lionel)

v3: Simplify workaround (Curro)

v4: Don't drop the existing WA (Curro)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: 22.0 <mesa-stable>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14947>
 2022-03-17 14:18:02 +00:00
Sagar Ghuge
6031ad4bf6 intel/fs: Add Wa_22013689345 
v2: Use a simpler framework (Lionel)

v3: Rebase, add task/mesh (Lionel)

v4: Fixup fence exec size (SIMDX -> SIMD1)

v5: Fix invalidate_analysis, add finishme comment (Curro)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: 22.0 <mesa-stable>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14947>
 2022-03-17 14:18:02 +00:00
Anuj Phogat
5cc4075f95 anv, iris: Add Wa_16011411144 for DG2 
v2: Use CS_STALL instead of FLUSH_ENABLE in Iris (Lionel)
    Add missing CS_STALL after SO_BUFFER change in Anv (Lionel)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Cc: 22.0 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14947>
 2022-03-17 14:18:02 +00:00
Juan A. Suarez Romero
c432bfe74b broadcom/ci: Update flake list 
Some of the tests marked as flake didn't show up as flakes for a long
time (more than 3 months). So likely they are already fixed.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15411>
 2022-03-17 13:56:41 +00:00
Connor Abbott
072fdcabcd tu: Enable UniformBufferUpdateAfterBind 
UBOs are now read at run-time via the preamble so this can be enabled.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
 2022-03-17 12:15:45 +00:00
Connor Abbott
9932ca8a3f ir3, turnip: Use ldc.k to push UBOs 
This reuses the same UBO analysis to do the pushing in the shader
preamble via the ldc.k instruction instead of in the driver via
CP_LOAD_STATE6. The const_data UBO is exempted as it uses a different
codepath that isn't as critical.

Don't do this on gallium because there are some regressions. Aztec Ruins
in particular regresses a bit, and nothing I've benchmarked benefits.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
 2022-03-17 12:15:45 +00:00
Connor Abbott
221a912b8c ir3: Refactor ir3_compiler_create() to take an options struct 
This will let us add more options without creating too much churn.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
 2022-03-17 12:15:45 +00:00
Connor Abbott
acba08b58f ir3: Implement and document ldc.k 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
 2022-03-17 12:15:45 +00:00
Connor Abbott
fccc35c2de ir3: Add preamble optimization pass 
Now that everything is plumbed through, we can tie it together.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
 2022-03-17 12:15:45 +00:00
Connor Abbott
986f7adfee ir3: Don't include preamble instructions in stats 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
 2022-03-17 12:15:45 +00:00
Connor Abbott
42e21c751b ir3: Insert frag coord code after preamble 
To match the pre-preamble behavior, and so that we can better schedule
it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
 2022-03-17 12:15:45 +00:00
Connor Abbott
b6fe69d855 ir3: Support prefetching with preambles 
Since the NIR pass runs very late, it needs to be aware of preambles,
and when creating the instruction we need to move it to the start block
so that RA doesn't overwrite it in the preamble.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
 2022-03-17 12:15:45 +00:00
Connor Abbott
00d7ad334a ir3/legalize: Handle inserting (ei) with preamble 
Make sure that shaders with a preamble are still considered
early-release so that we don't regress them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
 2022-03-17 12:15:45 +00:00
Connor Abbott
ccc64b7e00 ir3: Plumb through store_uniform_ir3 intrinsic 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
 2022-03-17 12:15:45 +00:00
Connor Abbott
944f4e6f8a ir3: Better assemble/disassemble stc 
Add in the type, even though it turns out to not be that useful. Add
in support for assembling it. Add some notes based on computerator
experiments. And add support for the indirect a1.x mode that's needed
for storing c64.x and later.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
 2022-03-17 12:15:45 +00:00
Connor Abbott
3244e659e0 ir3: Implement basic shader preamble intrinsics 
These will be used to implement the ir3-specific shader preamble
lowering in NIR. shps is conceptually similar to getone (although it
technically can't be duplicated) and shpe is similar to other barriers,
since it has to happen after any stores to the constant file in the
preamble. Add NIR intrinsics and plumbs them through ir3.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
 2022-03-17 12:15:45 +00:00
Connor Abbott
7ad57d9af1 ir3: Don't count reserved user consts in ubo_state::size 
Previously we included the reserved user consts (for Vulkan push
constants) as part of the pushed UBO contents, but that led to a problem
because when calculating the worst-case space for UBOs we didn't factor
in the reserved user consts. We'll have the same problem when doing the
same thing in the preamble optimization pass. Stop including the
reserved size in ubo_state::size, and have ir3_setup_consts() add it in
instead, so we won't forget to add it anywhere.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
 2022-03-17 12:15:45 +00:00
Connor Abbott
e274354204 ir3: Fix scan.macro valid flags 
Right now we don't support any. We could probably support const, but
that's not worth it because we could optimize a reduce of a const better
anyway.

Fixes: 1a78604d20 ("ir3: Add support for subgroup arithmetic")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
 2022-03-17 12:15:45 +00:00