Commit Graph

116855 Commits

Author SHA1 Message Date
Erik Faye-Lund
7034422389 zink: prepare for caching of renderpases/framebuffers
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Erik Faye-Lund
b458863c1e zink/spirv: implement loops
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Erik Faye-Lund
acdd12dae3 zink/spirv: implement discard
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Erik Faye-Lund
11ad9bfc35 zink/spirv: implement if-statements
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Erik Faye-Lund
8bbf86e7bc zink/spirv: prepare for control-flow
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Erik Faye-Lund
32aea77cfe zink/spirv: handle reading registers
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Erik Faye-Lund
f317105dd9 zink/spirv: implement some integer ops
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Dave Airlie
d2abe0ac61 zink/spirv: store all values as uint.
This adds bitcasting to uint everywhere for now,
and stores all spir-v ssa values as uints.

It also casts bool to 0/0xffffffff for now
(nir 1-bit bools may be coming in the future).

This fixes a lot of piglit tests to pass now

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Erik Faye-Lund
ac530c1ce2 zink: remove discard_if
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Dave Airlie
6d96578912 zink: query support (v2)
This at least passes piglit occlusion_query test for me here now.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Erik Faye-Lund
b533de12a5 zink: transform z-range
In vulkan, the Z-range of clip-space goes from 0..W instead of -W..+W
as is the case in OpenGL. So we need to transform the Z-range to
account for this.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Dave Airlie
9fa7400564 zink: add dri loader
export MESA_LOADER_DRIVER_OVERRIDE=zink should now work without using
swrast paths

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Erik Faye-Lund
4249e4a598 zink/spirv: implement point-sprites
This passes glsl-fs-pointcoord_gles2 from piglit.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Dave Airlie
c3bd0274c6 zink: ask for flatshade lowering
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Erik Faye-Lund
48f1f20a9d zink: detect presence of VK_KHR_maintenance1
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Erik Faye-Lund
8d46e35d16 zink: introduce opengl over vulkan
Here's zink, a so far pretty simple vulkan-gallium driver that is able
to translate some applications from OpenGL to Vulkan.

The compiler is quite limited for now, this will be improved on later.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 08:51:43 +00:00
Samuel Pitoiset
5912792501 radv: fix OpQuantizeToF16 for NaN on GFX6-7
Do not flush NaN to 0.

Fixes
dEQP-VK.spirv_assembly.instruction.compute.opquantize.propagated_nans

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-28 09:31:52 +01:00
Samuel Pitoiset
d82dfca872 radv: enable fast depth/stencil clears with separate aspects on GFX8
It's similar to GFX9+. Shadow of Mordor (Vulkan beta) hits that
path and it works fine.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-28 07:54:11 +00:00
Jordan Justen
66796a1787 iris: Mark aux-map BO as used by all batches
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 00:09:14 -07:00
Jordan Justen
2e6a7ced4d iris/gen12: Write GFX_AUX_TABLE base address register
Rework:
 * Move last_aux_map_state to iris_batch. (Nanley, Ken)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 00:09:14 -07:00
Jordan Justen
f046c6d090 iris: Map each surf to it's aux-surf in the aux-map tables
Rework: Nanley Chery
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 00:09:14 -07:00
Jordan Justen
d09db2d7b2 isl/gen12: 64k surface alignment
Reworks:
 * Update size for aux map change (Nanley)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 00:09:14 -07:00
Jordan Justen
f118ca2075 iris/bufmgr: Initialize aux map context for gen12
Reworks:
 * free gen_buffer in gen_aux_map_buffer_free. (Rafael)
 * lock around aux_map_bos accesses. (Ken)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 00:09:14 -07:00
Lionel Landwerlin
6af8a4acc4 anv: Add aux-map translation for gen12+
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 00:09:14 -07:00
Jordan Justen
7737f56544 anv/gen12: Write GFX_AUX_TABLE base address register
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-28 00:09:14 -07:00
Jordan Justen
109c96b322 genxml/gen12: Add AUX MAP register definitions
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 00:09:13 -07:00
Jordan Justen
d4a3299ba1 anv/gen12: Initialize aux map context
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-28 00:09:13 -07:00
Jordan Justen
0d0290bb3f intel/common: Add surface to aux map translation table support
Reworks:
 * Add ISL_FORMAT_B8G8R8X8_UNORM_SRGB to get_format_encoding (Nanley)
 * ralloc_free aux_map_buffer entries in gen_aux_map_finish. (Rafael)
 * verify_aligned_space => align_and_verify_space (Rafael)
 * Add mutex to aux-map code. (Rafael, Nanley)
 * Add gen_aux_map_fill_bos (Ken)
 * Make gen_aux_map_get_state_num lockless

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 00:09:13 -07:00
Jordan Justen
062022f2e4 anv: Implement aux-map allocator interface
This interface allows the aux-map code in the intel/common library to
allocate and free buffers.

Reworks:
 * free gen_buffer in gen_aux_map_buffer_free. (Rafael)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-10-28 00:09:13 -07:00
Jordan Justen
c848ab45f3 intel/common: Add interface to allocate device buffers
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 00:09:13 -07:00
Lionel Landwerlin
830cdaf3f0 intel/dev: store whether the device uses an aux map tables on devinfo
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 00:09:10 -07:00
Tapani Pälli
412badd059 i965: setup sized internalformat for MESA_FORMAT_R10G10B10A2_UNORM
Commit d2b60e433e introduced restrictions (as per GLES spec) on the
internal format. We need to setup a sized format for the texture image
so framebuffers created with that are considered complete.

This change fixes following Android CTS test in AHardwareBufferNativeTests
category:

   SingleLayer_ColorTest_GpuColorOutputAndSampledImage_R10G10B10A2_UNORM

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Fixes: d2b60e433e ("mesa/main: R10G10B10_(A2) formats are not color renderable in ES")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 07:13:10 +02:00
Eric Engestrom
32cff3781a tu: fix empty-body instruction
Fixes: 8d43e2b2de ("meson: add -Werror=empty-body to disallow `if(x);`")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-10-27 22:10:31 +00:00
Eric Engestrom
0581a86753 v3d: fix empty-body instruction
Fixes: 8d43e2b2de ("meson: add -Werror=empty-body to disallow `if(x);`")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-10-27 22:10:31 +00:00
Eric Engestrom
c2430f3edc radv: fix empty-body instruction
Fixes: 8d43e2b2de ("meson: add -Werror=empty-body to disallow `if(x);`")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-10-27 22:10:31 +00:00
Eric Engestrom
493903199c anv: fix empty-body instruction
Fixes: 8d43e2b2de ("meson: add -Werror=empty-body to disallow `if(x);`")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-10-27 22:09:14 +00:00
Jonathan Marek
521cdde8fc freedreno/a2xx: use sysval for pointcoord
Fixes a problem with shaders using gl_PointCoord.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reported-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-10-27 16:53:32 +00:00
Alyssa Rosenzweig
a0c0030075 pan/midgard: Disable precise occlusion queries
I thought there was hardware support for this, but it seems to broken,
or at least more complex than I believed.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-10-26 14:38:59 +00:00
Urja Rannikko
dff99ce7d5 panfrost: allocate bo for occlusion query results
This memory needs to still be available after all the drawing is done
and forgotten about, so cannot be transient.
Also clear the result so that no rendering returns a zero.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-10-26 14:38:25 +00:00
Alyssa Rosenzweig
728a975700 panfrost: Expose serialized NIR support
Serialized NIR is required for clover with the SPIR-V pipeline. With
this change and PAN_MESA_DEBUG=deqp, clinfo is able to successfully
probe panfrost.

Code from Nouveau (commit 7955fabcf8 by
Karol Herbst).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-10-26 13:17:42 +00:00
Alyssa Rosenzweig
afb0d08cb0 pipe-loader: Default to kmsro if probe fails
A device supported by kmsro will not automatically probe kmsro since the
driver name will be panfrost/lima/v3d/..., not "kmsro". Since kmsro is a
bit of a catch-all for generic (mostly embedded) GPUs, add a fallback on
kmsro for the dynamic loader.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
2019-10-26 13:17:42 +00:00
Alyssa Rosenzweig
4949876dd0 pipe-loader: Add kmsro pipe_loader target
kmsro is used by numerous embedded GPUs for a common winsys abstraction.
Let's add support for it for the dynamic pipe loader, so clover can
probe on these drivers.

We build the target with Panfrost. When other drivers need kmsro+clover,
we can revisit the build system part; my mesonfu is wanting.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
2019-10-26 13:17:42 +00:00
Jose Fonseca
ace5138548 scons: Fix force_scons parsing.
- Use parsed options instead of using ARGUMENTS directly.
- Handle the case of mingw cross compilation.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2003
2019-10-26 08:23:48 +01:00
Timothy Arceri
cff53da374 radv: enable secure compile support
Can be enabled via the environment variable which tells the
driver how many compilation threads are expected to be called,
and therefore how many forked processes the driver should
create.

For example we would expect to call fossilize replay with
something like this:

RADV_SECURE_COMPILE_THREADS=8 ./fossilize-replay --num-threads 8 \
--shader-cache-size 0 --ignore-derived-pipelines pipeline_cache.foz

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-26 13:04:12 +11:00
Timothy Arceri
57c95d2ce2 radv: a support for a secure compile fork at device creation
This added support for the fork, the installation of the seccomp
filter, and the main loop for the actual compilation to be called
from i.e. run_secure_compile_device().

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-26 13:04:12 +11:00
Timothy Arceri
3f2283b3e2 radv: add radv_secure_compile()
This function will be called by the parent process when doing a
secure compile. It first selects a free process to work with then
passes it all the information it needs to compile the pipeline.

Once the pipeline information has been passed to the secure
process, it then waits around to read/write any disk cache entries
required before exiting.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-26 13:04:12 +11:00
Timothy Arceri
07692f703f radv: for secure compile exit early from radv_shader_variant_create()
We don't have permission to be creating shared memory etc.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-26 13:04:12 +11:00
Timothy Arceri
5cd437b1ed radv: allow the secure process to read and write from disk cache
This allows the secure process to read and write to the disk cache
via the parent process. This commit just adds the functionality
needed for the secure process, the following commit will add the
functionality for the parent process.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-26 13:04:12 +11:00
Timothy Arceri
5d25aee005 radv: add radv_device_use_secure_compile() helper
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-26 13:04:12 +11:00
Timothy Arceri
d33f2165c9 radv: add some new members to radv device and instance for secure compile
These will be used by the following commits to hold information about
the forked secure compile processes.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-26 13:04:12 +11:00