Commit Graph

124030 Commits

Author SHA1 Message Date
Eric Engestrom
ba44990726 git_sha1_gen.py: fix whitespace
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5112>
2020-05-20 22:05:41 +00:00
Eric Engestrom
c909370117 git_sha1_gen.py: fix code style
Bare `except` are bad form as per PEP8.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5112>
2020-05-20 22:05:41 +00:00
Eric Engestrom
413c6f9905 git_sha1_gen.py: fix out-of-date comment
This hasn't been true since 7088622e5f ("buildsys: move file
regeneration logic to the script itself") almost 3 years ago.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5112>
2020-05-20 22:05:41 +00:00
Eric Engestrom
f68db81cbb anv: disable VK_EXT_calibrated_timestamps when the timestamp register is unreadable
When running in a virtual context, the timestamp register is unreadable
on Gen12+.
While we could work around this, that would result in very inaccurate
results for an extension where the whole point is accuracy, so let's
just disable the extension.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2797>
2020-05-20 21:49:10 +00:00
Eric Engestrom
a62ee262fd anv: replace magic | 1 with already #define'd name
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2797>
2020-05-20 21:49:10 +00:00
Eric Engestrom
e27f311c85 anv: pass the fd directly to anv_gem_reg_read()
This allows its use without the need for an anv_device.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2797>
2020-05-20 21:49:10 +00:00
Eric Anholt
6bf40c28c9 ci: Make a530's GLES3/31 fractional runs much more complete.
Now that we don't get scheduled to any 19mhz CPUs, the old GLES3 job went
from 12 minutes of deqp-runner runtime to 54s.  Increase how much of the
testsuite we cover in exchange, still keeping the runtime at 3-6 min
(compared to previous 10-17 min).  Since the tests we're running changed,
reset the xfails list.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5115>
2020-05-20 21:05:32 +00:00
Eric Anholt
6033c10092 ci: Disable SMP on the a5xx boards.
CPU0 comes up at some plausible freq, but the rest are at 19Mhz waiting
for cpufreq to come up, which has not been upstreamed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5115>
2020-05-20 21:05:32 +00:00
Andrii Simiklit
d1b7462849 i965/vec4: Ignore swizzle of VGRF for use by var_range_end()
Issue description from Matt's commit e7c376ad:
 "var_range_end(v, n) loops over the n components of variable number v and
  finds the maximum value, giving the last use of any component of v.
  Therefore it expects v to correspond to the variable associated with the
  .x channel of the VGRF.

  var_from_reg() however returns the variable for the first channel of the
  VGRF, post-swizzle.

  So, if the last register had a swizzle with y, z, or w in the swizzle
  component, we would read out of bounds. For any other register, we would
  read liveness information from the next register.

  The fix is to convert the src_reg to a dst_reg in order to call the
  dst_reg version of var_from_reg() that doesn't consider the swizzle."

Closes: #3003
Fixes: 48dfb30f ('intel/compiler: Move all live interval analysis results into vec4_live_variables')
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Andrii Simiklit <asimiklit.work@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4941>
2020-05-20 20:19:18 +00:00
Dave Airlie
10095387f5 r600/sfn: fix nop channel assignment.
this fixes a bunch of asserting tests on cayman

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5113>
2020-05-20 19:51:07 +00:00
Eric Engestrom
34718070ef docs: update calendar for 20.1.0-rc4
Adding another release candidate next week.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5134>
2020-05-20 21:45:49 +02:00
D Scott Phillips
81201e4617 anv/gen11+: Disable object level preemption
An unknown issue is causing vs push constants to become corrupted
during object-level preemption. For now, restrict to command
buffer level preemption to avoid rendering corruption.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5110>
2020-05-20 19:08:47 +00:00
Jonathan Marek
5a6beb6a24 freedreno: add adreno 650
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>
2020-05-20 18:24:28 +00:00
Jonathan Marek
72d7d2145c freedreno/a6xx: use RESOLVE_TS event
This is required on a650 to flush the GMEM store.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>
2020-05-20 18:24:28 +00:00
Jonathan Marek
e49748521e freedreno: reduce extra height alignment in a6xx layout
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>
2020-05-20 18:24:28 +00:00
Jonathan Marek
f6f8a19092 freedreno/a6xx: split up gmem/tile alignment requirements
RB_BLIT has a granularity of 16x4, but tile sizes must be 32x16 aligned.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>
2020-05-20 18:24:28 +00:00
Jonathan Marek
bf024c96ad freedreno/a6xx: don't use gmem_alignw for imported buffers
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>
2020-05-20 18:24:28 +00:00
Jonathan Marek
4b65fcb067 freedreno/a5xx: remove unused reference to gmem_alignw in layout code
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>
2020-05-20 18:24:28 +00:00
Jonathan Marek
aa2186db0e freedreno: move a4xx specific layout code to a4xx code
Every other gen has its own setup_slices

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>
2020-05-20 18:24:28 +00:00
Dylan Baker
5580322486 tests: Make tests aware of meson test wrapper
Meson 0.55.0 will set the MESON_EXE_WRAPPER environment variable to the
joined version of that wrapper if it is needed. Our tests that take
compiled targets as arguments can use that information to run cross
built binaries, or if there isn't a wrapper and we get an ENOEXEC, we
can skip the tests gracefully.

We try to use mesonlib.split_args, which handles windows arguments
better than python's builtin shlex module, but fall back to that if the
meson module isn't available for some reason.

Cc: 20.0 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5103>
2020-05-20 17:57:15 +00:00
Thong Thai
ef0d92459c gallium/auxiliary/vl: Fix compute shader scale_y for interlaced videos
Signed-off-by: Thong Thai <thong.thai@amd.com>
Fixes: 494b7ef0c1 ("gallium/auxiliary/vl: Fix compute shader scaling for non-square pixels")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5121>
2020-05-20 17:32:36 +00:00
Alyssa Rosenzweig
fc06b8b7dc pan/mdg: Optimize liveness computation in DCE
Rather than recompute liveness every block, compute it just once for the
whole shader, which ends up more efficient.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5123>
2020-05-20 17:06:34 +00:00
Alyssa Rosenzweig
c24dfc9da4 pan/mdg: Precompute mir_special_index
Rather than O(N) each call, we can precompute the whole set - also O(N)
- and then subsequent checks are O(1).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5123>
2020-05-20 17:06:34 +00:00
Alyssa Rosenzweig
4cf02b5d4a pan/mdg: Optimize pipelining logic
The test and rewrite were both accidentally O(N) to the shader size when
they should be O(1), so overall this takes the pass from O(N^2) to O(N).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5123>
2020-05-20 17:06:34 +00:00
Alyssa Rosenzweig
d39f95b75a pan/mdg: Emit fcsel when beneficial
If there are floating point modifiers, we emit fcsel instead of icsel
(and likewise if integer modifiers, icsel instead of fcsel) to minimize
redundant instructions.

total instructions in shared programs: 3628 -> 3626 (-0.06%)
instructions in affected programs: 139 -> 137 (-1.44%)
helped: 2
HURT: 0

total bundles in shared programs: 1886 -> 1885 (-0.05%)
bundles in affected programs: 19 -> 18 (-5.26%)
helped: 1
HURT: 0

total quadwords in shared programs: 3319 -> 3317 (-0.06%)
quadwords in affected programs: 127 -> 125 (-1.57%)
helped: 2
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5123>
2020-05-20 17:06:34 +00:00
Lionel Landwerlin
db9e16450d intel/aub_error_decoder: print driver identifier if found
You can find it right before the application batch :

HuC firmware: i915/kbl_huc_ver02_00_1810.bin
        status: fetch NONE, load NONE
        version: wanted 2.0, found 0.0
        header: offset 0, size 0
        uCode: offset 0, size 0
        RSA: offset 0, size 0
Driver identifier: i965 20.0.0-devel
--- batch buffer (rcs0 (submitted by glxgears [44455])) at 0x0000fffe ec000000
0xfffeec000000:  0x70000007:  MEDIA_VFE_STATE
0xfffeec000000:  0x70000007 : Dword 0
    DWord Length: 7
0xfffeec000004:  0x00000000 : Dword 1
    Per Thread Scratch Space: 0

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Lionel Landwerlin
64473fd8f7 anv: add identifier BO
A buffer added to all execbufs so that we can attribute a batch that
caused a hang to a particular driver.

v2: Reuse workaround BO

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Lionel Landwerlin
507b1ca10c i965: add identifier BO
A buffer added to all execbufs so that we can attribute a batch that
caused a hang to a particular driver.

v2: Reuse workaround BO

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Lionel Landwerlin
2a4c361b06 iris: add identifier BO
A buffer added to all execbufs so that we can attribute a batch that
caused a hang to a particular driver.

v2: Reuse workaround BO

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Lionel Landwerlin
805b32cab9 intel: add identifier for debug purposes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Lionel Landwerlin
e81de67d85 i965: store workaround_bo offset
This offset store the location where we read/write into the
workaround_bo. It will allow to select a different address later,
leaving the beginning of the buffer to some other use.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Lionel Landwerlin
07781f0afe iris: store workaround address
This will allow to select a different address later, leaving the
beginning of the buffer to some other use.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Lionel Landwerlin
33b452aae7 anv: store the workaround address
This will allow to select a different address later, leaving the
beginning of the buffer to some other use.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Lionel Landwerlin
0ff5b9e692 blorp: rename workaround address function
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Lionel Landwerlin
f36708b143 anv: fixup unwinding of device create failure
We appear to have the ordering mixed up a bit.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>
2020-05-20 15:58:22 +00:00
Icecream95
faf28b83fd panfrost: Enable PIPE_CAP_VERTEX_COLOR_UNCLAMPED
This tells Mesa to clamp vertex colours in the vertex shader.

This improves rendering in a number of games such as Extreme Tux
Racer and H-Craft Championships.

Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5075>
2020-05-20 15:14:28 +00:00
Andrii Simiklit
3725aa7b5d glsl_type: don't serialize padding bytes from glsl_struct_field
This should fix such valgrind warnings:
==37417== Uninitialised byte(s) found during client check request
==37417==    at 0x6183471: blob_write_bytes (blob.c:163)
==37417==    by 0x629785B: encode_type_to_blob (glsl_types.cpp:2760)
==37417==    by 0x61E68D8: write_variable (nir_serialize.c:293)
==37417==    by 0x61E6F6A: write_var_list (nir_serialize.c:421)
==37417==    by 0x61EBA7A: nir_serialize (nir_serialize.c:2018)
==37417==    by 0x5B5E007: serialize_nir_part (brw_program_binary.c:135)
==37417==    by 0x5B5E7F3: brw_serialize_program_binary (brw_program_binary.c:299)
==37417==    by 0x5FEF5FF: write_program_payload (program_binary.c:177)
==37417==    by 0x5FEF7BB: _mesa_get_program_binary_length (program_binary.c:225)
==37417==    by 0x5E3D31D: get_programiv (shaderapi.c:912)
==37417==    by 0x5E3F730: _mesa_GetProgramiv (shaderapi.c:1827)
==37417==    by 0x111DA0: program_binary_save_restore (shader_runner.c:686)
==37417==  Address 0x8f59481 is 81 bytes inside a block of size 480 alloc'd
==37417==    at 0x483B7F3: malloc (vg_replace_malloc.c:309)
==37417==    by 0x618CE67: ralloc_size (ralloc.c:123)
==37417==    by 0x618CF35: rzalloc_size (ralloc.c:155)
==37417==    by 0x618D245: rzalloc_array_size (ralloc.c:234)
==37417==    by 0x629041D: glsl_type::glsl_type(glsl_struct_field const*, unsigned int, glsl_interface_packing, bool, char const*) (glsl_types.cpp:148)
==37417==    by 0x6293EC3: glsl_type::get_interface_instance(glsl_struct_field const*, unsigned int, glsl_interface_packing, bool, char const*) (glsl_types.cpp:1271)
==37417==    by 0x604C878: (anonymous namespace)::per_vertex_accumulator::construct_interface_instance() const (builtin_variables.cpp:365)
==37417==    by 0x6050722: (anonymous namespace)::builtin_variable_generator::generate_varyings() (builtin_variables.cpp:1568)
==37417==    by 0x60509CA: _mesa_glsl_initialize_variables(exec_list*, _mesa_glsl_parse_state*) (builtin_variables.cpp:1600)
==37417==    by 0x6149AE9: _mesa_ast_to_hir(exec_list*, _mesa_glsl_parse_state*) (ast_to_hir.cpp:131)
==37417==    by 0x60706D6: _mesa_glsl_compile_shader (glsl_parser_extras.cpp:2222)
==37417==    by 0x5E3DC16: _mesa_compile_shader (shaderapi.c:1211)

==37417== Use of uninitialised value of size 8
==37417==    at 0x529AE13: ??? (in /usr/lib/x86_64-linux-gnu/libz.so.1.2.11)
==37417==    by 0x6184075: util_hash_crc32 (crc32.c:127)
==37417==    by 0x5FEF401: write_program_binary (program_binary.c:95)
==37417==    by 0x5FEF8BC: _mesa_get_program_binary (program_binary.c:252)
==37417==    by 0x5E40E22: _mesa_GetProgramBinary (shaderapi.c:2411)
==37417==    by 0x4914057: stub_glGetProgramBinary (piglit-dispatch-gen.c:24737)
==37417==    by 0x111E4A: program_binary_save_restore (shader_runner.c:704)
==37417==    by 0x11F765: piglit_display (shader_runner.c:5112)
==37417==    by 0x499082F: run_test (piglit_fbo_framework.c:52)
==37417==    by 0x4980E89: piglit_gl_test_run (piglit-framework-gl.c:229)
==37417==    by 0x110DA9: main (shader_runner.c:72)

v2: - decode_glsl_struct_field_from_blob and
    encode_glsl_struct_field should be `static`
    ( Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> )
v3: - we can get rid of `struct packed_struct_field_flags`
    ( Tapani Pälli <tapani.palli@intel.com> )
    - we can get rid of `unsigned __pad: 15` bitfield
    ( Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> )

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Andrii Simiklit <asimiklit.work@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5054>
2020-05-20 14:15:00 +00:00
Jonathan Marek
0d9996e223 turnip: enable 422_UNORM formats
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4590>
2020-05-20 13:22:12 +00:00
Jonathan Marek
d070a7ba0c turnip: implement VK_KHR_sampler_ycbcr_conversion
Most changes based on radv, some simplification, since we don't need to
sample multiple planes, 422_UNORM/420_UNORM formats will be supported
directly using the hardware formats for those.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4590>
2020-05-20 13:22:12 +00:00
Jonathan Marek
70502f071c freedreno/registers: document 422_UNORM and 420_UNORM formats
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4590>
2020-05-20 13:22:12 +00:00
Jonathan Marek
75d7ee8029 util/format: translate 422_UNORM and 420_UNORM vulkan formats
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4590>
2020-05-20 13:22:12 +00:00
Lionel Landwerlin
d0e11231a4 intel/perf: repurpose INTEL_DEBUG=no-oaconfig
We initially used this debug option to mean "don't bother registering
the OA configuration into the kernel".

This change makes this option suppress any interaction with the
i915/perf interface. This is useful when debugging self modifying
batches with performance queries while running on the intel_mi_runner.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin
2001a80d4a anv: Implement VK_KHR_performance_query
This has the same kernel requirements are VK_INTEL_performance_query

v2: Fix empty queue submit (Lionel)

v3: Fix autotool build issue (Piotr Byszewski)

v4: Fix Reset & Begin/End in same command buffer, using soft-pin &
    relocation on the same buffer won't work currently. This version
    uses a somewhat dirty trick in anv_execbuf_add_bo (Piotr Byszewski)

v5: Fix enumeration with null pointers for either pCounters or
    pCounterDescriptions (Piotr)
    Fix return condition on enumeration (Lionel)
    Set counter uuid using sha1 hashes (Lionel)

v6: Fix counters scope, should be COMMAND_KHR not COMMAND_BUFFER_KHR (Lionel)

v7: Rebase (Lionel)

v8: Rework checking for loaded queries (Lionel)

v9: Use new i915-perf interface

v10: Use anv_multialloc (Jason)

v11: Implement perf query passes using self modifying batches (Lionel)
     Limit support to softpin/gen8

v12: Remove spurious changes (Jason)

v13: Drop relocs (Jason)

v14: Avoid overwritting .sType in
     VkPerformanceCounterKHR/VkPerformanceCounterDescriptionKHR (Lionel)

v15: Don't copy the entire
     VkPerformanceCounterKHR/VkPerformanceCounterDescriptionKHR (Jason)
     Reuse anv_batch rather than custom packing (Jason)

v16: Fix missing MI_BB_END in reconfiguration batch
     Only report the extension with kernel support (perf_version >= 3)

v17: Some cleanup of unused stuff

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin
ceb822f9e0 intel/perf: reuse offset specified in the query
The current code relies on the order of the function
gen_perf_query_result_accumulate() to match the descriptions written
by gen_perf.py. Let's just reuse the offset specified in the python
script.

v2: Use accumlator offsets more (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin
63c193e921 anv: use a query filled by the perf code
We're about to use the offset fields from the query object. We can't
just use a made up object.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin
93924ab091 intel/perf: report whether the platform supported
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin
fe8e8e5099 intel/perf: add counter category to generated code
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin
c36933e081 intel/perf: add helper to compute metrics from counters
The produced array tells use what metric to enable for a given pass.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin
a7890f559b intel/perf: emit counter units in generated code
We'll use this coming extension.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00
Lionel Landwerlin
d15369332f intel/perf: compute number of passes for a set of counters
We want to compute the number of passes required to gather performance
data about a set of counters.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
2020-05-20 14:02:27 +03:00