Commit Graph

111449 Commits

Author SHA1 Message Date
Erik Faye-Lund
b9e9d701dc mesa/main: correct extension-checks for GL_PRIMITIVE_RESTART_FIXED_INDEX
This shouldn't be allowed in GLES 1/2.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-05-29 10:54:09 +02:00
Erik Faye-Lund
34ade0dc7c mesa/main: correct extension-checks for GL_BLEND_ADVANCED_COHERENT_KHR
KHR_blend_equation_advanced_coherent isn't exposed on OpenGL ES 1.x, so
we shouldn't allow its enums there either.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-05-29 10:54:09 +02:00
Erik Faye-Lund
c0dabc6192 mesa/main: correct extension-checks for GL_FRAMEBUFFER_SRGB
This enum shouldn't be allowed on OpenGL ES 1.x, so let's instead
use the extenion-helpers, and check for desktop and gles extensions
separately.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-05-29 10:54:09 +02:00
Erik Faye-Lund
a33ff7876f mesa/main: correct extension-checks for MESA_tile_raster_order
This extension isn't enabled for GLES 1.x, so we shouldn't allow the
state there. Let's use the extension-helpers instead of CHECK_EXTENSION
for this.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-05-29 10:54:09 +02:00
Erik Faye-Lund
bf91d6ae4a mesa/main: make the CONSERVATIVE_RASTERIZATION_NV checks consistent
This just makes the logic of the checks for this enum the same for
gl{Enable,Disable} and for glIsEnabled. They are already functionally
the same, so this is just a minor code-cleanup.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-05-29 10:54:09 +02:00
Erik Faye-Lund
00c683bc8e mesa/main: make the PRIMITIVE_RESTART_NV checks consistent
{En,Dis}ableClientState(PRIMITIVE_RESTART_NV) should only work on
compatibility contextxs. While we're at it, modernize the code a bit,
by using the extension helpers instead of open-coding.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-05-29 10:54:09 +02:00
Samuel Pitoiset
d3771ccaa3 radv: use view format when selecting the resolve path for subpasses
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-29 08:53:48 +02:00
Samuel Pitoiset
017170a785 radv: always use view format when performing subpass resolves
It makes sense to use the image view formats when resolving
inside subpasses, while we have to use the image formats for
normal resolves.

Original patch by Philip Rebohle.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110348
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-29 08:53:46 +02:00
Samuel Pitoiset
eaeaad25f7 radv: sync before resetting a pool if there is active pending queries
Make sure to sync all previous work if the given command buffer
has pending active queries. Otherwise the GPU might write queries
data after the reset operation.

This fixes a bunch of new dEQP-VK.query_pool.* CTS failures.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-29 08:47:54 +02:00
Kenneth Graunke
bc273dece2 intel/decoder: Use get_state_size() over guessed counts in more cases
This makes the following packets use actual driver provided sizes rather
than guessing an arbitrary number:

  - CC_VIEWPORT
  - SF_CLIP_VIEWPORT
  - BLEND_STATE
  - COLOR_CALC_STATE
  - SCISSOR_RECT

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
2019-05-28 13:44:16 -07:00
Mike Lothian
29ea92e6a1 meson: Link Gallium drivers with ld_args_build_id
Link all Gallium drivers with ld_args_build_id to prevent failures in
Iris that uses GNU_BUILD_ID

Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=110757
Fixes: 4756864cdc "iris: Start wiring up on-disk shader cache"

Signed-off-by: Mike Lothian <mike@fireburn.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-05-28 13:37:36 -07:00
Lionel Landwerlin
366811bedb nir/lower_non_uniform: safely iterate over blocks
This fixes a problem where the same instruction gets replaced twice.
This was happening when the replaced instruction would be at the end
of a block.

Replacement of :

   if ssa_8 {
                ....
      intrinsic bindless_image_store (ssa_44, ssa_16, ssa_0, ssa_15) (5, 0, 34836, 32) /* image_dim=Buf */ /* image_array=false */ /* format=34836 */ /* access=32 */
   }

Would be :

   if ssa_8 {
      loop {
         vec1 32 ssa_47 = intrinsic read_first_invocation (ssa_44) ()
         vec1 1 ssa_48 = ieq ssa_47, ssa_44
         if ssa_48 {
            loop {
               vec1 32 ssa_49 = intrinsic read_first_invocation (ssa_44) ()
               vec1 1 ssa_50 = ieq ssa_49, ssa_44
               if ssa_50 {
                  intrinsic bindless_image_store (ssa_44, ssa_16, ssa_0, ssa_15) (5, 0, 34836, 32) /* image_dim=Buf */ /* image_array=false */ /* format=34836 */ /* access=32 */
                  break
               } else {
        ....
   }

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3bd5457641 ("nir: Add a lowering pass for non-uniform resource access")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-05-28 20:23:16 +01:00
Samuel Pitoiset
47a10edefb radv: allocate more space in the CS when emitting events
If the driver waits for CP DMA to be idle and emit an EOP event
we need more space.

This fixes a crash with Quake Champions.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-28 16:56:17 +02:00
Kenneth Graunke
6a9e39d44b iris: Ask st to vectorize our IO.
(Technically this is common code, but it doesn't affect i965 or anv.)

Improves performance of GFXBench5/gl_tess_off on Skylake GT4e at 1080p
by 9.3933% +/- 0.0305157% by eliminating all spilling in the GS.

Improves performance of GFXBench5/gl_4_off (Car Chase) on Skylake GT4e
at 1080p by 0.325208% +/- 0.0842233% (n=18).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-05-28 01:06:48 -07:00
Kenneth Graunke
c31b4420e7 st/nir: Re-vectorize shader IO
We scalarize IO to enable further optimizations, such as propagating
constant components across shaders, eliminating dead components, and
so on.  This patch attempts to re-vectorize those operations after
the varying optimizations are done.

Intel GPUs are a scalar architecture, but IO operations work on whole
vec4's at a time, so we'd prefer to have a single IO load per vector
rather than 4 scalar IO loads.  This re-vectorization can help a lot.

Broadcom GPUs, however, really do want scalar IO.  radeonsi may want
this, or may want to leave it to LLVM.  So, we make a new flag in the
NIR compiler options struct, and key it off of that, allowing drivers
to pick.  (It's a bit awkward because we have per-stage settings, but
this is about IO between two stages...but I expect drivers to globally
prefer one way or the other.  We can adjust later if needed.)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-05-28 01:06:48 -07:00
Mathias Fröhlich
1d0a8cf40d mesa: Prevent classic swrast crash on a surfaceless context v2.
This fixes the egl_mesa_platform_surfaceless piglit test as well
as the new egl_ext_device_base piglit test on classic swrast.

v2: Fix swrast surfaceless contexts on the driver side.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-05-28 08:27:16 +02:00
Samuel Pitoiset
15cb19ed6f radv add radv_get_resolve_pipeline() in the compute path
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-28 08:17:26 +02:00
Samuel Pitoiset
469258c3b1 radv: cleanup the compute resolve path for subpass
This makes use of radv_meta_resolve_compute_image() by filling
a VkImageResolve region instead of duplicating code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-28 08:17:23 +02:00
Timothy Arceri
d2b0246741 radeonsi: add drirc workaround for American Truck Simulator
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110711
2019-05-28 08:47:44 +10:00
Timothy Arceri
11e16ca7ce Revert "st/mesa: expose 0 shader binary formats for compat profiles for Qt"
This reverts commit 55376cb31e.

It's been over a year and both QT 5.9.5 and 5.11.0 contained a fix for the
original issue. It seems i965 only ever applied this workaround to the
18.0 branch.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-05-28 08:46:50 +10:00
Lionel Landwerlin
2042f22e28 anv: fix apply_pipeline_layout pass for arrays of YCbCr descriptors
When using the binding tables to access arrays of YCbCr descriptors we
did not consider the offset of the accessed element. We can't do a
simple multiple because the binding table entries are tightly packed.

For example element 0 of the array could use 2 entries/planes and
element 1 could use 2 entries/planes.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3bb8768b9d ("anv: toggle on support for VK_EXT_ycbcr_image_arrays")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-05-27 22:47:53 +01:00
Marek Olšák
fccced57cf radeonsi: clean up winsys creation
- unify the code
- choose radeon or amdgpu based on the DRM version, not based on which one
  succeeds first
2019-05-27 15:26:06 -04:00
Marek Olšák
bb5d82bd06 radeonsi: allow query functions for compute-only contexts 2019-05-27 15:26:06 -04:00
Marek Olšák
b257956021 ac: treat Mullins as Kabini, remove the enum
it's the same design
2019-05-27 15:10:51 -04:00
Christian Gmeiner
37af75f88c etnaviv: rs: choose clear format based on block size
Fixes following piglit and does not introduce any regressions.
  spec@ext_packed_depth_stencil@fbo-depth-gl_depth24_stencil8-blit

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2019-05-27 20:55:11 +02:00
Vasily Khoruzhick
af0de6b91c lima/ppir: implement discard and discard_if
This commit also adds codegen for branch since we need it
for discard_if.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-05-27 07:39:03 -07:00
Samuel Pitoiset
7a7be61398 radv: ignore the loadOp if the first use of an attachment is a resolve
Based on ANV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-27 13:52:39 +02:00
Samuel Pitoiset
ff27eb509a radv: always dirty the framebuffer when restoring a subpass
The old code was not wrong because the transitions performed
after the resolves should re-emit the framebuffer if needed.

This change is mostly a no-op but it improves consistency
regarding other meta operations that need to save/restore subpasses.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-27 13:52:36 +02:00
Samuel Pitoiset
9af15986b0 radv: add radv_clear_htile() helper
This helper will be useful for clearing HTILE after some
depth/stencil resolves.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-27 13:52:34 +02:00
Chenglei Ren
13b38ca1e4 anv/android: fix missing dependencies issue during parallel build
The libmesa_anv_gen* modules require anv_extensions.h, patch makes sure
it gets generated as a dependency before building them.

Signed-off-by: Chenglei Ren <chenglei.ren@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
2019-05-27 10:13:17 +03:00
Samuel Pitoiset
2d2e7954c3 radv: tidy up GetQueryPoolResults for occlusion queries
Just move the block that checks the availability bit into the
switch like other query types.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-27 08:50:55 +02:00
Kenneth Graunke
b5fa3abfc2 iris: Don't flag IRIS_DIRTY_URB after BLORP operations unless it changed
We already flag IRIS_DIRTY_URB when we change it, but we were
additionally flagging it on every BLORP operation, even if we didn't.
2019-05-26 17:45:18 -07:00
Dave Airlie
7fe5a8e874 Revert "mesa: unreference current winsys buffers when unbinding winsys buffers"
This reverts commit 12bf7cfecf.

This commits caused lots of problems:
https://bugs.freedesktop.org/show_bug.cgi?id=110721
https://bugs.freedesktop.org/show_bug.cgi?id=110761

Fixes: 12bf7cfecf ("mesa: unreference current winsys buffers when unbinding winsys buffers")
Pushing without review as we need to get it into next stable.
2019-05-27 09:36:28 +10:00
Alyssa Rosenzweig
659aa3dd65 panfrost/midgard: Implement fneg/fabs/fsat
Fix a regression I inadvertently caused by acking typeless movs before
implementing/pushing this *whistles*

Nothing to see here, move along folks.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-26 03:16:37 +00:00
Qiang Yu
1dc593e9b9 lima: fix lima_blit with non-zero level source resource
lima_blit will do blit between resources with different levels.
When blit from a level!=0 source, it will sample from that level
of resource as texture.

Current texture setup won't respect level when not mipmap filter.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
2019-05-25 12:41:44 +08:00
Qiang Yu
54490b0b36 lima: fix render to non-zero level texture
Current implementation won't respect level of surface to render.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
2019-05-25 12:41:31 +08:00
Dylan Baker
9838185056 editorconfig: Fix meson style
The syntax was wrong, resulting in it not working at all.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-05-24 18:44:18 +00:00
Chia-I Wu
ea1e0acfd0 virgl: remove an incorrect check in virgl_res_needs_flush
Imagine this

  resource_copy_region(ctx, dst, ..., src, ...);
  transfer_map(ctx, src, 0, PIPE_TRANSFER_WRITE, ...);

at the beginning of a cmdbuf.  We need to flush in transfer_map so
that the transfer is not reordered before the resource copy.  The
check for "vctx->num_draws == 0 && vctx->num_compute == 0" is not
enough.  Removing the optimization entirely.

Because of the more precise resource tracking in the previous
commit, I hope the performance impact is minimized.  We will have to
go with perfect resource tracking, or attempt a more limited
optimization, if there are specific cases we really need to optimize
for.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-05-24 17:37:40 +00:00
Chia-I Wu
56f9b60e50 virgl: reemit resources on first draw/clear/compute
This gives us more precise resource tracking.  It can be beneficial
because glFlush is often followed by state changes.  We don't want
to reemit resources that are going to be unbound.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-05-24 17:37:40 +00:00
Chia-I Wu
424ec2356b virgl: add missing emit_res for SO targets
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-05-24 17:37:40 +00:00
Roland Scheidegger
d4e8a44bf6 gallivm: fix default cbuf info.
The default null_output really needs to be static, otherwise the values
we'll eventually get later are doubly random (they are not initialized,
and even if they were it's a pointer to a local stack variable).
VMware bug 2349556.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-05-24 19:22:50 +02:00
Roland Scheidegger
84f3f1cf00 scons: fix build with llvm 9.
The x86asmprinter component is gone, and things seem to work by just
removing it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110707

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-05-24 18:28:28 +02:00
Tomeu Vizoso
9fe1a925e2 panfrost: Dereference sampled texture
We are currently leaking resources if they were sampled from. Once we
are done with a sampler, we should dereference that resource.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 16:50:09 +02:00
Tomeu Vizoso
3c81010213 panfrost: ci: Avoid pulling Docker image on every run
Jump over the container stage if we haven't changed any of the files
that involved in building the container images.

This saves 1-2 minutes in each run and helps conserve resources.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 16:50:09 +02:00
Jason Ekstrand
f2dc0f2872 nir: Drop imov/fmov in favor of one mov instruction
The difference between imov and fmov has been a constant source of
confusion in NIR for years.  No one really knows why we have two or when
to use one vs. the other.  The real reason is that they do different
things in the presence of source and destination modifiers.  However,
without modifiers (which many back-ends don't have), they are identical.
Now that we've reworked nir_lower_to_source_mods to leave one abs/neg
instruction in place rather than replacing them with imov or fmov
instructions, we don't need two different instructions at all anymore.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Rob Clark <robdclark@chromium.org>
2019-05-24 08:38:11 -05:00
Jason Ekstrand
22421ca7be nir/builder: Merge nir_[if]mov_alu into one nir_mov_alu helper
Unless source modifiers are present, fmov and imov are the same.
There's no good reason for having two helpers.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 08:38:11 -05:00
Jason Ekstrand
cd73b6174b nir/lower_to_source_mods: Stop turning add, sat, and neg into mov
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 08:38:11 -05:00
Jason Ekstrand
2a39788d03 nir/source_mods: Add a helpers for setting source modifiers
It's potentially a tiny bit less efficient but the helpers make it much
easier to sort out the rules for updating source modifiers.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 08:38:11 -05:00
Jason Ekstrand
8ffbb54405 intel: Implement abs, neg, and sat in the back-end
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 08:38:11 -05:00
Jason Ekstrand
4fde459563 intel/nir: Call alu_to_scalar one last time before out-of-ssa
A few of our very late passes can end up generating vectors accidentally
so we need to get rid of them.  The only known case of this is the ffma
peephole which generates fneg and fabs as vectors.  Currently, they're
not a problem because they get turned into fmov which the back-end
compiler knows how to handle as a vector.  That's about to change.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 08:38:11 -05:00