The in kernel texture check fails because of both
bit11 flags being set on 16x16 textures. It tuns out
that these bits are still set and not cleared in the
pp_txpitch field of the texture. The attached patch
at least helps for this case on my machine. It clears
the bit 11 from the pitch field if the texture is smaller
and masks out that hight bits on the conventional width
and height field.
Fixes bug 24584
size was being calculated based on 3 bytes per pixel with 24 bit depth
instead of 4 bytes. This caused corruption in the bottom 25% of objects.
This finishes fixing the menu/text corruption in compiz/kde4.
Signed-off-by: Robert Noland <rnoland@2hip.net>
Setting the wrong bo size resulting in an incomplete
read cache flush when reading the texture. This fixes the
compiz text corruption.
[agd5f: take hw pitch alignment into account]
Again, last valid address, not first invalid address. Fixes regression
in 255e5be265 that the kernel now catches
and caused piglit draw_elements_base_vertex to fail.
It's the address of the last valid byte, not the address of the first
invalid byte.
This should also fix problems with rendering with the new sanity checks in
the kernel.
Before, if we called glXMakeCurrent() to change a context's window binding
while an FBO was bound, we weren't updating the intel->driDrawable and
intel->driReadDrawable fields. This could cause us to dereference a null
pointer elsewhere.
The non-KMS interface is to blame here. In theory, a proper fix
could be produced that works for the KMS interface only, but it
require cleaning a lot of mess. Easier to just do it right in r300g.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
Once we've freed a miptree, we won't see any more state cache requests
that would hit the things that pointed at it until we've let the miptree
get released back into the BO cache to be reused. By leaving those
surface state and binding table pointers that pointed at it around, we
would end up with up to (500 * texture size) in memory uselessly consumed
by the state cache.
Bug #20057
Bug #23530
This is similar to what r300 does inside the driver, but I've added it as
a generic option since it seems most hardware will want it.
Fixes piglit nv-init-zero-reg.vpfp and nv-init-zero-addr.vpfp.
If there happened to be a bound VBO when intel_generate_mipmap() was
called we blew up because of a bad vertex array pointer.
Fixes regnumonline, bug 23859.
Radeon generic scissors code had problem that some of code was using exclusive
and some inclusive bottom right corner. Only r600 driver is using exclusive
coordinate so changed generic code to pass inclusive coordinate and r600 driver
changes BR coordinate to be exclusive.
- max texture size is 8k, but mesa doesn't support
that at the moment.
- attempt to set shader limits to what the hw actually
supports
- clean up some old r300 cruft
- no need to explicitly disable irqs. This is fixed
in the drm now.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
- MUL_LIT is ALU.Trans instruction
- some Trans instructions can take 3 arguments
- don't clobber dst.x, use dst.z as temp, it'll get written correct
value in last insn
- respect source swizzles
1D tile span support for depth/stencil/color/textures
Z and stencil buffers are always tiled, so this fixes
sw access to Z and stencil buffers. color and textures
are currently linear, but this adds span support when we
implement 1D tiling.
This fixes the text in progs/demos/engine and progs/tests/z*
