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Author SHA1 Message Date
Jianxun Zhang
b6f9702cf1 iris: Disable PAT-based compression on depth surfaces (xe2) 
Fix: Piglit
PIGLIT_PLATFORM="gbm" piglit/bin/getteximage-depth -auto -fbo

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
e835b53a03 anv: Don't enable compression on external bos (xe2) 
Fix:

dEQP-VK.synchronization.cross_instance.suballocated.
write_draw_indexed_read_blit_image.image_128x128_r16
_uint_binary_semaphore_fence_fd

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
9cd97b6137 iris: Add more restrictions on compression (Xe2) 
Also move the declaration of a local variable to where
it is going to use.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
0b75f89f57 anv: Don't enable compression with modifiers (xe2) 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
66fa1c5ddd iris: Limit FCV_CCS_E to platforms that enable it 
We want to keep aux state always in compressed and no clear,
but the write behavior of FCV will change it to compressed and
clear. Reuse old CCS_E on Xe2 to workaround it.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8785

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
df006bba02 iris: Update aux state for color fast clears (xe2) 
The texturing and rendering preparation functions restrict
fast clear support in some cases to account for limitations
on prior platforms. Instead of updating those checks to avoid
resolves on Xe2, we can bypass them by representing the aux
state of a fast-cleared surface as compressed-no-clear. This
is valid because there is no longer a bit pattern which
references a clear value stored outside of the aux surface.

Suggested by Nanley Chery <nanley.g.chery@intel.com>

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
1c92b31888 intel/genxml,blorp,common: Update 3DSTATE_PS command (xe2) 
From Bspec 56423 (r58507), the legacy full resovling and
partial resolving options are gone since Xe2. They also
cause hang on Xe2 if not disabled.

Some suggested code from Nanley Chery <nanley.g.chery@intel.com> is
included.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
4dfc3367fc blorp: Pass down fast clear color value (xe2) 
Also add a quote of Bspec for previous platforms.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
3269d505e7 blorp: Get fast clear rectangle of non-MSAA surfaces (xe2) 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
3b89bdb96e isl: Don't set clear values or their address (xe2) 
The render surface state doesn't have these features any
more since Xe2.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Qiang Yu
93f790b04a nir: fix clip cull distance lowering metadata preserve 
indirect store lowering will use if/else which changes
the control flow of the shader.

Fixes: 110887de2b ("nir: Add a new pass to lower array dereferences on vectors")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29894>
 2024-06-26 01:22:12 +00:00
Qiang Yu
09b4ba27a3 nir: fix lower array to vec metadata preserve 
indirect store lowering will change control flow,
so we should not preserve control flow metadate
when it's present.

Fixes: 35b8f6f40b ("nir: Add a new pass to lower array dereferences on vectors")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29894>
 2024-06-26 01:22:12 +00:00
Jianxun Zhang
7be1912625 isl: Update render CMF mapping (xe2) 
Update mapping between render target surface formats and
compression formats.

Some preexisting correct mappings are also re-ordered to
the order of types in the spec for an easier verification
(top to bottom and left to right).

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29905>
 2024-06-25 23:02:14 +00:00
Jordan Justen
a985576755 isl: Implement isl_get_render_compression_format for xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29905>
 2024-06-25 23:02:14 +00:00
Jordan Justen
bb6e8cab79 isl: Move isl_get_render_compression_format in isl_genX_helpers.h 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29905>
 2024-06-25 23:02:14 +00:00
Ian Romanick
2bbd0fd9da intel/brw/xe2+: Add LNL cooperative matrix configurations 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:17:47 -07:00
Ian Romanick
6b678d32cb nir: dpas_intel second source can have different number of components 
The number of components for the second source is -1 to avoid validation of
its value. Some supported configurations will have the component count of
that matrix different than the others.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:17:47 -07:00
Ian Romanick
556e78f737 intel/brw/xe2+: Allow vec16 for cooperative matrix 
Xe2 will allow a B matrix large enough that it will be stored in a
vec16.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:17:47 -07:00
Ian Romanick
b6236dd8f3 intel/brw/xe2+: Adjust DPAS lowering to DP4A to accommodate larger GRF and SIMD16 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:17:47 -07:00
Ian Romanick
77ef241577 intel/brw/xe2+: Scale size_written by reg_unit for DPAS 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:17:47 -07:00
Ian Romanick
e368b8e01b intel/brw/xe2+: Adjust size_read() for DPAS 
v2: Remov "DG2" from a comment because it applies to DG2 and
Xe2. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:17:47 -07:00
Ian Romanick
b051602754 intel/brw/xe2+: Catch invalid uses of writes_accumulator earlier 
It turns out the problem I was trying to catch in be4fa59a72
("intel/brw: Clear write_accumulator flag when changing the
destination") also came from the DPAS lowering pass itself. Checking for
invalid uses of the feature in fs_validate helped detect the problem.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:17:47 -07:00
Ian Romanick
7a773ac53e intel/brw: Major rework of lower_cmat_load_store 
The original goal was to get rid of a bunch of the magic constants
sprinkled through the function. Once I did that, I realized that there
was a lot my symmertry between the row-major and column-major paths
possible.

It's +6 lines of code, but about 15 of those lines are comments
explaining things that were not obvious in the original code.

v2: Save duplicated condition in a variable with a meaningful
name. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 14:16:48 -07:00
Ian Romanick
ea6e10c0b2 intel/brw: Temporarily disable result=float16 matrix configs 
Even though the hardware does not naively support these configurations,
there are many potential benefits to advertising them. These
configurations can theoretically use half the memory bandwidth for loads
and stores. For large matrices, that can be the limiting in performance.

The current implementation, however, has a number of significant
problems.

The conversion from float16 to float32 is performed in the driver during
conversion from NIR. As a result, many common usage patterns end up
doing back-to-back conversions to and from float16 between matrix
multiplications (when the result of one multiplication is used as the
accumulator for the next).

The float16 version of the matrix waste half the possible register
space. Each float16 value sits alone in a dword. This is done so that
the per-invocation slice of an 8x8 float16 result matrix and an 8x8
float32 result matrix will have the same number of elements. This makes
it possible to do straightforward implementations of all the unary_op
type conversions in NIR.

It would be possible to perform N:M element type conversions in the
backend using specialized NIR intrinsics. However, per #10961, this
would be very, very painful. My hope is that, once a suitable resolution
for that issue can be found, support for these configs can be restored.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28834>
 2024-06-25 13:52:12 -07:00
Juston Li
33dd38f9d5 anv/android: set ANV_BO_ALLOC_EXTERNAL for imported AHW 
This fixes some cacheline flush artifacts

Signed-off-by: Juston Li <justonli@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29882>
 2024-06-25 20:21:27 +00:00
Daniel Stone
9eeaa4618f egl/gbm: Enable RGBA configs 
Doing this is harmless since we operate on an allowlist of pipe_configs
anyway.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29837>
 2024-06-25 19:30:12 +00:00
Daniel Stone
94e15d0f64 egl/surfaceless: Enable RGBA configs 
Doing this is harmless since we operate on an allowlist of pipe_configs
anyway.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29837>
 2024-06-25 19:30:12 +00:00
Daniel Stone
5ca85d75c0 dri: Fix BGR format exclusion 
The check we had for BGR vs. RGB formats was testing completely the
wrong thing. Fix it so we can restore the previous set of configs we
expose to the frontend, which also fixes surfaceless platform on s390x.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes: ad0edea53a ("st/dri: Check format properties from format helpers")
Closes: mesa/mesa#11360
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29837>
 2024-06-25 19:30:12 +00:00
Job Noorman
8f2533c356 ir3: set rounding mode for all floating point conversions 
The rounding mode was only set for a subset of floating point
conversions. This patch sets it for all of them.

Fixes all the dEQP-VK.*.float_controls.* CTS tests.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29843>
 2024-06-25 17:00:59 +00:00
Job Noorman
93db751c63 ir3: print rounding mode for cov 
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29843>
 2024-06-25 17:00:59 +00:00
Erik Faye-Lund
8c2bfa279d panvk: support x11 wsi 
This seems to be enough to get XCB working. From looking at what other
drivers does, it seems likely that XLib will just work, so let's enable
that as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29878>
 2024-06-25 15:49:42 +00:00
José Roberto de Souza
2d29dee889 intel/perf: Extend intel_perf_query_result_read_gt_frequency() to gfx 20 
BSpec 62720 states that the previous and current offsets remains the
same as previous gfx versions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29899>
 2024-06-25 14:16:45 +00:00
José Roberto de Souza
0a6fe638f3 intel/perf: Add INTEL_PERF_QUERY_FIELD_TYPE_SRM_OA_PEC 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29899>
 2024-06-25 14:16:45 +00:00
José Roberto de Souza
6e1852981b intel/perf: Add LNL OA XML 
Also added pec_offset to struct intel_perf_query_info and two new
hw variables needed by this XML, those changes are required to at
least compile with this new XML.

pec_offset will be set in the next patches.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29899>
 2024-06-25 14:16:45 +00:00
José Roberto de Souza
5b8b4f7878 intel/dev: Add engine_class_supported_count to intel_device_info 
Next patch will need to frequently get the count of supported engine
for compute and copy engines, so to reduce the overhead of doing
KMD queries at every call here caching this information into
intel_device_info struct.

With that ANV and Iris would need to set this information as intel/dev
can't depend on intel/common, so here adding a single function
to update intel_device_info with all fields filled by intel/common
functions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29899>
 2024-06-25 14:16:45 +00:00
José Roberto de Souza
2f2a0bc083 intel/perf: Add assert to check if allocated enough query fiels 
Xe2 platforms will have way more query fields and allocation of that
will need to be increased but first lets add a function to return the
max_fields and assert if tried to access more query fields then
allocated.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29899>
 2024-06-25 14:16:45 +00:00
José Roberto de Souza
0a51842f7a intel/perf: Change order of if blocks 
Most places we follow the newest GFX version first, so doing that
here.
No changes in behavior exepected.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29899>
 2024-06-25 14:16:45 +00:00
Michel Dänzer
2dec0cbe01 egl/dri: Use packed pipe_format 
This is consistent with __DRI_IMAGE_FORMAT_ARGB8888 and the rest of
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27709 .

This makes no difference with little endian, it does with big endian
though.

Fixes: dcbf61f5df ("egl/dri: Use pipe_format instead of DRI_IMAGE_FORMAT")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29781>
 2024-06-25 12:27:17 +00:00
Erik Faye-Lund
fdd204538b ci: build docs using meson 
To avoid having to inflate the image here even further, let's just add
what we need to the the normal x86 Alpine build image, and use that.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11494>
 2024-06-25 10:59:54 +00:00
Erik Faye-Lund
1e7636fbb1 meson: allow specifying html-docs-path 
This will allow us to decide where to install docs. Useful for GitLab
Pages on CI.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11494>
 2024-06-25 10:59:54 +00:00
Erik Faye-Lund
e31dde13d1 meson: error when missing hawkmoth 
Hawkmoth is a hard depedency, and building without it will lead to
errors. Give a friendly error early on.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11494>
 2024-06-25 10:59:54 +00:00
Erik Faye-Lund
2063003457 docs: automatically generate depfile 
We need to regenerate the docs if any of the rst-files are changed. So
let's add a simple extension to generate a depfile, so meson will pick
up any changes needed.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11494>
 2024-06-25 10:59:54 +00:00
Erik Faye-Lund
c26d4ee44f meson: build html-docs 
This allows us to build our Sphinx-based documentation from the meson
build system.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11494>
 2024-06-25 10:59:54 +00:00
Erik Faye-Lund
69809a0384 docs: allow out-of-tree docs build 
Hawkmoth runs from the build-directory, which makes sense. However, we
set up a bunch of source-relative include paths, which will break if we
don't build in-tree.

Let's make these relative to the source-tree instead. We can deduce the
source-root from the parent directory of the current file.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11494>
 2024-06-25 10:59:54 +00:00
Erik Faye-Lund
09c1f3b9fd docs: use os.pardir 
I'm not really sure if this ever matters in real-life, but os.pardir
exists and we should probably use it instead of hard-coding it to '..'.

Fixes: 67485efd65 ("docs: prepare for hawkmoth")
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11494>
 2024-06-25 10:59:54 +00:00
Erik Faye-Lund
e5f0481351 docs: metadatas -> metadata 
"Metadata" is already plural, so adding the s at the end is not correct.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29879>
 2024-06-25 10:51:27 +00:00
Erik Faye-Lund
4bb6816d26 docs: pusbuf -> pushbuf 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29879>
 2024-06-25 10:51:27 +00:00
Erik Faye-Lund
372bd9366e docs: pluggins -> plug-ins 
The extra 'g' is probably a typo, but we also use a dash to separate
elsewhere, so let's be consistent.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29879>
 2024-06-25 10:51:27 +00:00
Erik Faye-Lund
0945b24df7 docs: acress -> across 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29879>
 2024-06-25 10:51:27 +00:00
Erik Faye-Lund
bc61409192 docs: attachements -> attachments 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29879>
 2024-06-25 10:51:27 +00:00