Commit Graph

192484 Commits

Author SHA1 Message Date
Rohan Garg
fe387e14b5 anv: use the WA infrastructure when emitting WA 16013994831
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30295>
2024-07-22 13:43:39 +00:00
Rhys Perry
3aa29c47b9 nir/instr_set: hash tex sources commutatively
I'm not sure if two otherwise equal texture instructions ever have sources
in different orders, but they should be considered equal.

ministat of nir_opt_cse:
    N           Min           Max        Median           Avg        Stddev
x   9      6.586801      6.718673      6.682875     6.6621411   0.047817119
+   9      6.519098      6.609235      6.552997     6.5605604   0.028879587
Difference at 95.0% confidence
	-0.101581 +/- 0.0394755
	-1.52475% +/- 0.585928%
	(Student's t, pooled s = 0.0395)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30145>
2024-07-22 11:04:01 +00:00
Rhys Perry
b7ceb9d327 nir/instr_set: stop sorting phi sources
This is faster.

ministat of nir_opt_cse:
    N           Min           Max        Median           Avg        Stddev
x   9      6.724212       6.84511      6.788336     6.7873378   0.034363882
+   9      6.586801      6.718673      6.682875     6.6621411   0.047817119
Difference at 95.0% confidence
	-0.125197 +/- 0.0416115
	-1.84456% +/- 0.609248%
	(Student's t, pooled s = 0.0416374)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30145>
2024-07-22 11:04:01 +00:00
Rhys Perry
8b328443e3 nir/instr_set: combine XXH32 calls
ministat of nir_opt_cse:
    N           Min           Max        Median           Avg        Stddev
x   9      7.393408      7.490593      7.434056     7.4338972   0.028150325
+   9      6.724212       6.84511      6.788336     6.7873378   0.034363882
Difference at 95.0% confidence
	-0.646559 +/- 0.0313916
	-8.69745% +/- 0.407925%
	(Student's t, pooled s = 0.0314111)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30145>
2024-07-22 11:04:01 +00:00
Pierre-Eric Pelloux-Prayer
159a3edd80 egl,gbm,glx: fix log message spam
Based on the other similar logs we only want to log when extensions
is NULL.
Use this opportunity to indicate the source of the log and remove
the extra ')' at the end of each line.

Fixes: 50fc7cc290 ("glx: directly link to gallium")
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30257>
2024-07-22 10:09:34 +00:00
Pierre-Eric Pelloux-Prayer
a55b9c0c60 radeonsi: consider DBG(NO_TILING) when filtering modifiers
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30257>
2024-07-22 10:09:34 +00:00
Pierre-Eric Pelloux-Prayer
94f2b3f7bc radeonsi: consider PIPE_BIND_LINEAR when filtering modifiers
If PIPE_BIND_LINEAR is set the only valid modifier we can use is
DRM_FORMAT_MOD_LINEAR.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30257>
2024-07-22 10:09:34 +00:00
Pierre-Eric Pelloux-Prayer
f12ccea6c7 radeonsi: reject modifiers with DCC when NO_EXPORTED_DCC is used
Otherwise AMD_DEBUG=noexporteddcc will be ignored when modifier are
used.
Similarly to AMD_DEBUG=nodcc handling, this makes the application
unable to import buffers with DCC as well - the alternative would be
to implement the filtering only in the texture creation path, so in
the si_modifier_supports_resource function.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30257>
2024-07-22 10:09:34 +00:00
Pierre-Eric Pelloux-Prayer
0c868aa94a amd: use a valid size for ac_pm4_state allocation
If max_dw is smaller than the pm4 array the allocation size would be
smaller than sizeof(ac_pm4_state).

Fixes: 428601095c ("ac,radeonsi import PM4 state from RadeonSI")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30257>
2024-07-22 10:09:34 +00:00
Eric Engestrom
547de1e928 v3d/ci: mark spec@amd_performance_monitor@vc4 tests as flaky
Turns out it was not fixed, it just happened to pass a bunch of times in
a row, but it actually fails randomly, so mark it as such.

Fixes: 4696e9c49b ("v3d/ci: mark spec@amd_performance_monitor@vc4 tests as fixed")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30290>
2024-07-22 10:56:09 +02:00
Juan A. Suarez Romero
4215d50384 v3d: add new clear blitter op
A specific clear_surface blitter operation is required, because in this
case we need to save framebuffer information, but not in standard clear,
as we are currently doing.

This fixes a leak in depthstencil surface, which happens because we were
storing saving it as part for the framebuffer information, but the
blitter clear wasn't restoring it because it wasn't required (only it
is required in clearing a surface).

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30240>
2024-07-22 08:11:57 +00:00
Juan A. Suarez Romero
7158950a6f v3d: use operations to specify what to save in blitter
So far, in order to know what we need to save before using the blitter
utility, we use a boolean to know if we are going to do a blit or not,
and if we need to take in account conditional rendering or not.

In other to allow to specify more operations than blit or not, use an
enum to define what operation we would like to do, and based on that
what information we need to store.

This also merge the conditional rendering as part of these operations.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30240>
2024-07-22 08:11:57 +00:00
Christian Gmeiner
c83330cde0 etnaviv: isa: left shift is 3 bit long
Blob generates such a shift for piglit's
generated_tests/cl/builtin/int/builtin-int-abs-1.0.generated.cl

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30232>
2024-07-22 07:12:28 +00:00
Icenowy Zheng
5f22e152ad gallivm: orcjit: use atexit to release LPJit singleton at exit
Valgrind will report some memory possibly lost because of this singleton
(it's dynamically allocated when it is first accessed).

Use atexit() to register a handler that releases this singleton.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30216>
2024-07-21 23:17:17 +00:00
Icenowy Zheng
3423e73cec gallivm: orcjit: keep the ownership of tm for LPJit
The ownership of the TargetMachine object is released when LPJit
singleton is constructed, leads to a slight memory loss detectable.

Keep the ownership by saving the unique pointer as another class member
named tm_unique.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30216>
2024-07-21 23:17:17 +00:00
David Heidelberg
dc6e6d7a2b freedreno: Enable Adreno 306A
Enable the Adreno 306A that is found on the QM215 SoC (Qualcomm 215).

The GPU marketing name is Adreno 308.

Kernel patch: https://lore.kernel.org/linux-arm-msm/20240528-a306a-v1-1-03a66dacd8c7@gmail.com/

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29401>
2024-07-21 21:31:06 +00:00
Eric Engestrom
5c5df9376f venus: initialize bitset in CreateDescriptorPool()
Fixes: de5879447b ("Track bitset when create descriptor pool")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30286>
2024-07-21 17:44:05 +00:00
Eric Engestrom
324ccd7430 nak: fix meson typo
Fixes: 95bff5ca5b ("nak: Add minimum bindgen requirement")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30288>
2024-07-21 17:58:53 +02:00
Faith Ekstrand
0cc23b6524 nak: Move creation of nak_shader_info to ShaderBin::new()
This makes ShaderBin a bit more self-contained since it can now be
created from just a compiled shader and info.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30283>
2024-07-20 14:40:26 -05:00
Faith Ekstrand
618dfc73e6 nak: Move a few more things to VtgIoInfo
This moves clip/cull and XFB and uses the recorded attributes to figure
out writes_layer and writes_point_size.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30283>
2024-07-20 14:40:26 -05:00
Faith Ekstrand
f39b645c66 nak: Rework fragment shader stage info
This adds a FragmentShaderStageInfo, moves uses_kill and does_interlock
there, and adds fields for API depth test bits.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30283>
2024-07-20 14:40:26 -05:00
Faith Ekstrand
d96fe18547 nak: Plumb tessellation parameters through ShaderStageInfo
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30283>
2024-07-20 14:40:26 -05:00
Faith Ekstrand
c4c9bfdebd nak: Drop the nvfuzz binary
A much better version now exists as part of
https://gitlab.freedesktop.org/gfxstrand/nv-shader-tools

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30283>
2024-07-20 14:40:23 -05:00
Yiwei Zhang
bb7632128b venus: only request ring thread prio for TLS ring
Mainly to leave main ring thread prio to default.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30279>
2024-07-20 17:27:24 +00:00
Faith Ekstrand
cc82f80dcb nak/nir: Split 64-bit conversions pre-Volta
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30281>
2024-07-20 16:53:38 +00:00
Faith Ekstrand
574239c948 nak/sm50: Implement OpCCtl
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30281>
2024-07-20 16:53:38 +00:00
Faith Ekstrand
6fd427bf6e nak: Lower fsqrt in NIR on Maxwell A and earlier
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30281>
2024-07-20 16:53:38 +00:00
Faith Ekstrand
9b4a005bf8 nak/sm50: Implement OpPixLd
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30281>
2024-07-20 16:53:38 +00:00
Faith Ekstrand
69be07b191 nak/sm50: Various encoding fixes
Most of this is code clean-ups and unifications.  A few things were
missing proper legalization.  Some of it was just plain wrong.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30281>
2024-07-20 16:53:38 +00:00
Faith Ekstrand
549fada593 nak/sm50: Improve encoding of OpFFma
OpFFma has another form that allows a cbuf in src2 which we weren't
taking into account.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30281>
2024-07-20 16:53:38 +00:00
Faith Ekstrand
cfef5a9329 nak/sm50: Support AtomOp::CmpExch
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30281>
2024-07-20 16:53:38 +00:00
Faith Ekstrand
7d1b1f5d3a nak: Add an AtomCmpSrc to AtomOp::CmpExch
Pre-Volta, OpAtom works like OpSuAtom where the comparison value and the
data are packed into a vector.  We need some way of expressing this in
the IR.  We could have a separate OpAtom instruction but that seems
unnecessary.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30281>
2024-07-20 16:53:38 +00:00
Faith Ekstrand
da4e368a6f nak: Implement ineg on sm50
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30281>
2024-07-20 16:53:38 +00:00
Faith Ekstrand
71d8126e1b nak/sm50: Split IAdd2 into IAdd2 and IAdd2X
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30281>
2024-07-20 16:53:38 +00:00
Faith Ekstrand
d2177f4764 nvk: Don't advertise sparse residency on Maxwell A
Fixes: 48803ac53d ("nvk: enable sparse residency features")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30281>
2024-07-20 16:53:38 +00:00
Faith Ekstrand
a888e83c3a nvk: Fix indirect cbuf binds pre-Turing
nvk_cmd_buffer_push_indirect() takes bytes, not dwords.

Fixes: ee29a8d1cd ("nvk: Upload cbufs based on the cbuf_map")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30281>
2024-07-20 16:53:38 +00:00
Daniel Almeida
66954d997d nouveau/headers: Add an nv_push crate in Rust
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28255>
2024-07-20 16:36:30 +00:00
Daniel Almeida
63770a163a nouveau/headers: Add a Rust struct for each method
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28255>
2024-07-20 16:36:30 +00:00
Daniel Almeida
591b5da49b nouveau/headers: Run rustfmt on generated files
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28255>
2024-07-20 16:36:30 +00:00
Sushma Venkatesh Reddy
2f6919e6c2 intel/clflush: Utilize clflushopt in intel_invalidate_range
On MTL ChromeOS boards, during AI based video conference, we were
observing a lot of overhead from invalidations. Upon debug, it was found
that we were using clflush in this function and that isn't efficient.

With this change, while executing compute workloads like zoo models, we
are getting ~25% performance improvements in a best case scenario.

Rework:
 * Jordan: Call intel_clflushopt_range() rather than
   __builtin_ia32_clflushopt() because intel_mem.c is not compiled
   with -mclflushopt.

Backport-to: 24.1 24.2
Signed-off-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30238>
2024-07-20 16:10:16 +00:00
Aleksi Sapon
fd0592afd3 gallivm: Fix LLVMPipe codegen issues discovered on Apple Silicon
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Roland Scheidegger <roland.scheidegger@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30108>
2024-07-20 15:36:24 +00:00
M Henning
2f49284cfa nak: Rename num_barriers to num_control_barriers
Hopefully this is a little more clear.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30180>
2024-07-20 15:20:49 +00:00
M Henning
aac97b22ae nak: Don't mix up two types of barrier
This part of the shader header is used for control flow barriers (like
glsl barrier()), not reconvergence barriers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30180>
2024-07-20 15:20:49 +00:00
Icenowy Zheng
ca087e2027 zink: reject Imagination proprietary driver w/o geometryShader
On some low-end GPUs (e.g. BXE/BXM series), the Imagination proprietary
Vulkan driver do not implement geometryShader feature, which is required
by Zink currently to smoothen lines. In addition, these vulkan drivers
shipped are usually not robust enough to run Zink at all, and
frequently fail with crashes.

Reject these drivers.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30280>
2024-07-20 22:03:54 +08:00
Daniel Stone
bed6e0d691 build: Check for PyYAML in Meson build
Closes: #11540
Fixes: ccc6442d6f ("u_format: Rewrite format table to use YAML")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30272>
2024-07-20 08:05:44 +00:00
Jessica Clarke
149e8bff52 meson: egl: Build egl_dri2 driver even for plain DRI
Despite its name, egl_dri2 works under plain DRI without DRI2, and the
old autotools build system built it when $enable_dri = yes, with no
check for DRI2. This fixes the build for GNU/Hurd, which supports DRI,
but doesn't have DRM and thus no DRI2 support.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/587>
2024-07-20 06:53:43 +00:00
Jessica Clarke
ec55a6c329 Revert "meson: fix with_dri2 definition for GNU Hurd"
This reverts commit ad862c36e5.

This change does not work, because libdrm is required if with_dri2 is
true. Moreover, we don't want all of DRI2 on Hurd, we just want the
egl_dri2 driver, as done by autotools. So first revert this to stop
trying to build all of DRI2.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/587>
2024-07-20 06:53:42 +00:00
Jessica Clarke
8461776a09 Revert "meson: Do not require libdrm for DRI2 on hurd"
This reverts commit 2fd85105c6.

Despite its name, egl_dri2 works under plain DRI without DRI2, and the
old autotools build system built it when $enable_dri = yes, with no
check for DRI2. A future commit will adapt meson.build to follow that
approach rather than this hackier one.

Note that the case removed in the second hunk is already dead code,
since system_has_kms_drm is false on GNU/Hurd, and could have been
dropped as part of 66d2ae0386 ("meson: forcefully disable libdrm when
host doesn't have it").

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/587>
2024-07-20 06:53:42 +00:00
Francisco Jerez
49144ebcf9 iris/gfx12.5: Pass non-empty push constant data to PS stage for TBIMR workaround.
Note that this bug leading to GPU hangs hasn't been reproduced on GL
so far, workaround is mainly included for completeness.

Fixes: 57decad976 ("intel/xehp: Enable TBIMR by default.")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30031>
2024-07-20 01:13:19 +00:00
Francisco Jerez
ff3c3792b4 anv/gfx12.5: Pass non-empty push constant data to PS stage for TBIMR workaround.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10728
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11399
Fixes: 57decad976 ("intel/xehp: Enable TBIMR by default.")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30031>
2024-07-20 01:13:19 +00:00