Commit Graph

87313 Commits

Author SHA1 Message Date
Dave Airlie
a5d10844ee radv: refactor descriptor set userdata emission out.
This just moves this into a separate function.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-12-07 23:25:18 +00:00
Dave Airlie
f847676990 radv: pass pipeline to constant flush function
I'll need this later rather than just the layout.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-12-07 23:25:15 +00:00
Dave Airlie
eb2ba5c8df radv: consolidate compute pipeline flushing (v1.1)
This just moves some common code into a utility function
to avoid having to change multiple places later.

v1.1: rename function to better reflect what it does. (Bas)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-12-07 23:24:53 +00:00
Marek Olšák
13c34cf8ca radeonsi: wait for outstanding LDS instructions in memory barriers if needed
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-07 19:40:29 +01:00
Marek Olšák
16ba04d6de tgsi: fix the src type of TGSI_OPCODE_MEMBAR
It's a literal integer. The next commit will need this.

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-07 19:40:29 +01:00
Marek Olšák
16f49c16c7 radeonsi: wait for outstanding memory instructions in TCS barriers
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-07 19:40:29 +01:00
Marek Olšák
15e96c70b0 radeonsi: allow specifying simm16 of emit_waitcnt at call sites
The next commit will use this.

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-07 19:40:29 +01:00
Marek Olšák
57b9d75af5 radeonsi: write shader descriptors into hang reports
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-07 19:40:29 +01:00
Marek Olšák
6caa558ca6 radeonsi: check for sampler state CSO corruption
It really happens.

v2: declare "magic" in debug builds only

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
2016-12-07 19:40:03 +01:00
Marek Olšák
f2b0c66c3c radeonsi: properly declare context sampler states
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-07 18:46:54 +01:00
Marek Olšák
38d4859b94 radeonsi: fix incorrect FMASK checking in bind_sampler_states
Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-07 18:46:54 +01:00
Marek Olšák
b3a2aa9cba radeonsi: always restore sampler states when unbinding sampler views
Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-07 18:46:54 +01:00
Marek Olšák
d205faeb6c radeonsi: take LDS into account for compute shader occupancy stats
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-07 18:46:54 +01:00
Marek Olšák
132b69c4ed st/mesa: round lod_bias to a multiple of 1/256
This reduces the number of sampler states 3.6x in Batman Arkham: Origins.
(from ~7200 to ~2000)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-07 18:46:54 +01:00
Marek Olšák
4b0d8b2da0 gallium: decrease the size of pipe_sampler_state fields
We've had unused bits.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-12-07 18:46:54 +01:00
Marek Olšák
6dc96de303 cso: don't release sampler states that are bound
This fixes random radeonsi GPU hangs in Batman Arkham: Origins (Wine) and
probably many other games too.

cso_cache deletes sampler states when the cache size is too big and doesn't
check which sampler states are bound, causing use-after-free in drivers.
Because of that, radeonsi uploaded garbage sampler states and the hardware
went bananas. Other drivers may have experienced similar issues.

Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-12-07 18:46:54 +01:00
Jordan Justen
e9133dd90e i965: Increase max texture to 16k for gen7+
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98297
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 09:00:49 -08:00
Jordan Justen
d6526d7247 intel/blorp_blit: Add split_blorp_blit_debug switch
Enabling this debug switch causes surface shrinking to happen by
default, and lowers the surface size limit which causes blorp blits to
be split.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 09:00:49 -08:00
Jordan Justen
da381ae647 intel/blorp_blit: Enable splitting large blorp blits
Detect when the surface sizes are too large for a blorp blit. When it
is too large, the blorp blit will be split into a smaller operation
and attempted again.

For gen7, this fixes the cts test:

ES3-CTS.gtf.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit

It will also enable us to increase our renderable size from 8k x 8k to
16k x 16k.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 09:00:49 -08:00
Jordan Justen
efea8e7244 intel/blorp_blit: Move RGB=>R conversion to follow blit splitting
In blorp_copy, when RGB surfaces are copied, we convert the
destination surface to a Red only surface, but 3 times as wide. This
introduces an implicit restriction of "mod 3" for the destination
width.

It is easier to handle the blorp split buffer offsetting with the
original RGB surface, and do the RGB=>R after this.

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 09:00:49 -08:00
Jordan Justen
edf3113aed intel/blorp_blit: Adjust blorp surface parameters for split blits
If try_blorp_blit() previously returned that a blit was too large,
shrink_surface_params() will be used to update the surface parameters
for the smaller blit so the blit operation can proceed.

v2:
 * Use double instead of float. (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 09:00:49 -08:00
Jordan Justen
12e0a6e259 intel/blorp_blit: Split blorp blits if they are too large
We rename do_blorp_blit() to try_blorp_blit(), and add a return error
if the surface size for the blit is too large. Now, do_blorp_blit() is
rewritten to try to split the blit into smaller operations if
try_blorp_blit() fails.

Note: In this commit, try_blorp_blit() will always attempt to blit and
never return an error, which matches the previous behavior. We will
enable the size checking and splitting in a future commit.

The motivation for this splitting is that in some cases when we
flatten an image, it's dimensions grow, and this can then exceed the
programmable hardware limits. An example is w-tiled+MSAA blits.

v2:
 * Use double instead of float. (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 09:00:49 -08:00
Jordan Justen
b74d4f6ca0 intel/blorp_blit: Create structure for src & dst coordinates
This will be useful for splitting blits into smaller sizes.

We also make the coordinates of type double rather than float. Since
we will be splitting and scaling the coordinates, we might require
extra precision in the calculations.

v2:
 * Use double instead of float. (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 09:00:49 -08:00
Edward O'Callaghan
a77426fd92 vulkan: use STATIC_ASSERT instead of static_assert
Following the spirit of commit 23d1799f, fixes compilation
warnings on Android build due to lack of C11 features.

Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 22:32:38 +11:00
Lionel Landwerlin
e9f17e9fb0 i965: enable INTEL_conservative_rasterization on Gen9+
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
2016-12-07 11:02:19 +00:00
Lionel Landwerlin
039d836d6e mesa: add support for GL_INTEL_conservative_rasterization
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
2016-12-07 11:02:16 +00:00
Plamena Manolova
0ff74a8990 i965: Add i965 plumbing for ARB_post_depth_coverage for i965 (gen9+).
This extension allows the fragment shader to control whether values in
gl_SampleMaskIn[] reflect the coverage after application of the early
depth and stencil tests.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-07 11:01:50 +00:00
Plamena Manolova
8481386892 mesa: Add GL and GLSL plumbing for ARB_post_depth_coverage for i965 (gen9+).
This extension allows the fragment shader to control whether values in
gl_SampleMaskIn[] reflect the coverage after application of the early
depth and stencil tests.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
2016-12-07 11:01:50 +00:00
Nicolai Hähnle
d3931a355f radeonsi: fix isolines tess factor writes to control ring
Fixes piglit arb_tessellation_shader/execution/isoline{_no_tcs}.shader_test.

Cc: mesa-stable@lists.freedesktop.org
2016-12-07 11:21:32 +01:00
Kenneth Graunke
9871bde351 i965: Drop redundant key->outputs_written initialization.
This was already set to the same value earlier.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-12-06 22:14:58 -08:00
Kenneth Graunke
09ffc5c84f i965: Initialize "separate" flag in VUE maps.
This was uninitialized, which resulted in weird looking printouts where
it appeared that the TCS output and TES input patch URB entries differed
in SSO/non-SSO layout.  There is no "separable" layout for both, as
they're tied together.

It should have no other actual effect.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-12-06 22:14:58 -08:00
Ian Romanick
b87039499b nir: In split_var_copies_block, uint, int, and bool types cannot be matrices
Noticed while adding support for 64-bit integer types.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-06 17:30:38 -08:00
Tom Stellard
4c8c13b356 radeonsi: Use amdgcn intrinsics for fs interpolation
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-07 00:42:40 +00:00
Rob Clark
a9383ae6d6 freedreno/a5xx: fix draw packet size with index buffer
gpuaddr of idx buffer is now two dwords (64b).

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06 18:01:31 -05:00
Rob Clark
ec24f009ca freedreno/a5xx: gmem bypass mode
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06 18:01:31 -05:00
Rob Clark
85a3057f65 freedreno/a5xx: fix emit_string_marker()
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06 18:01:31 -05:00
Rob Clark
c1e9cca696 freedreno: pitch alignment should match gmem alignment
Deal w/ differing gmem tile size alignment between generations, and make
sure texture pitch matches.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06 18:01:31 -05:00
Rob Clark
8f4da2ff63 freedreno/a5xx: more formats
Bunch of stuff we can at least turn on for vbo formats.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06 18:01:31 -05:00
Rob Clark
b337099849 freedreno/a5xx: fix fragface
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06 18:01:31 -05:00
Rob Clark
f143eeaffa freedreno/a5xx: fix fragcoord
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06 18:01:31 -05:00
Rob Clark
f5c5f76255 freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06 18:01:31 -05:00
Rob Clark
3ec4d1f809 freedreno/a5xx: fix alpha test
GRAS_SU_DEPTH_PLANE_CNTL doesn't in fact seem to be anything to do with
alpha test.  This fixes xonotic and (other than some iommu faults) gets
gnome-shell working.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06 18:01:31 -05:00
Rob Clark
2b305725e2 freedreno/a5xx: fix VPC_VAR[n].DISABLE bits
We don't need varying interpolators enabled for pos/psize out of the VS
(despite the fact that they show up in VS_OUT map), so emit these before
we append pos/psize to the linkage.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06 18:01:31 -05:00
Nanley Chery
72db1570b4 anv/TODO: Document sampling from HiZ
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-06 14:51:30 -08:00
Kenneth Graunke
05a4e3a009 i965: Don't force SSO layout for VS->TCS.
This was a hack which worked around the VS and TCS disagreeing on their
shared interface due to the lack of varying packing.  In particular, it
was needed by Piglit's tcs-input-read-array-interface test.

However, that was just one case where things could go awry, so the
previous commit forcibly made interfaces match.  This hack is no longer
necessary.

It also seems to be broken, though I'm not sure why.  It fixes Piglit
regressions in spec/arb_shader_image_load_store/semantics from commit
ec1f159ac8.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98893
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-12-06 12:36:21 -08:00
Kenneth Graunke
44fd85d8eb i965: Unify shader interfaces explicitly.
A while ago, I made i965 start compiling shaders independently.  The VUE
map layouts were based entirely on each shader's input/output bitfields.
Assuming the interfaces match, this works out well - both sides will
compute the same layout, and outputs are correctly routed to inputs.

At the time, I had assumed that the linker would guarantee that the
interfaces match.  While it usually succeeds, it unfortunately seems
to fail in some cases.

For example, Piglit's tcs-input-read-array-interface test has a VS
output array with two elements, but the TCS only reads one.  The linker
isn't able to eliminate the unused element from the VS, which makes the
interfaces not match.

Another case is where a shader other than the last writes clip/cull
distances.  These should be demoted to ordinary varyings, but they
currently aren't - so we think they still have some special meaning,
and prevent them from being eliminated.

Fixing the linker to guarantee this in all cases is complicated.  It
needs to be able to optimize out dead code.  It's tied into varying
packing and other messiness.  While we can certainly improve it---and
should---I'd rather not rely on it being correct in all cases.

This patch ORs adjacent stages' input/output bitfields together,
ensuring that their interface (and hence VUE map layout) will be
compatible.  This should safeguard us against linker insufficiencies.

Fixes line rendering in Dolphin, and the Piglit test based on it:
spec/glsl-1.50/execution/geometry/clip-distance-vs-gs-out.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97232
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-12-06 12:34:23 -08:00
Jason Ekstrand
eb7b51d62a genxml/gen9: Change the default of MI_SEMAPHORE_WAIT::RegisterPoleMode
We would really like it to be false as that's what you get on hardware that
doesn't have RegisterPoleMode (Sky Lake for example).  While we're at it,
we change it to a boolean.  This fixes dEQP-VK.synchronization.smoke.events
on Broxton.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
2016-12-06 11:35:13 -08:00
Roland Scheidegger
8ac3c1bf1a gallivm: optimize 16bit->32bit gather path a bit
LLVM can't really optimize anything which crosses scalar/vector boundaries,
so help a bit with some particular gather operations when the width is
expanded (only do it for 16->32bit expansion for now), by doing expansion
after fetch. That is probably a better solution anyway even if llvm would
recognize it, makes for cleaner IR...

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-12-06 20:06:06 +01:00
Roland Scheidegger
fd5f420fbb gallivm: handle 16bit float fetches in lp_build_fetch_rgba_soa
Note that we really want to _never_ reach the bottom of the function, which
resorts to AoS fetch.
Half floats can be handled just like other formats which fit into 32bit
vectors (so, only 1x16 and 2x16 formats, albeit with more channels things
are not THAT bad), with minimal plumbing. I've seen code size go down nearly
by a factor of 3 for a complete texture sampling function (including bilinear
filtering) using R16F.
(What we should do for everything not special cased is to do AoS gather,
shuffle/shift things into SoA vectors, and then do the conversion there.
Otherwise it's particularly bad with 1 or 2 channel formats - that r16f
format with either 4 or 8-wide vectors was still doing one element at a
time, essentially doing exactly the same work as for rgba16f. Also replacing
the channels with SWIZZLE0/1 (particularly the latter) adds even more
work, as it has to be done per aos vector, and not just straightforward
at the end with the SoA vector.)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-12-06 20:06:06 +01:00
Roland Scheidegger
775a244645 util: (trivial) ETC1 meets the criteria for fitting into unorm8
Just like other similar compressed formats.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-12-06 20:06:06 +01:00