This matches the byte based offset of brw_load_register_mem*.
The function is also moved into intel_batchbuffer.c like
brw_load_register_mem*.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Pretty much only happens if shader variant compile fails. But in this
case, if we haven't emitted cmdstream, we don't want to set needs_flush.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
This was always a bit overly complicated, and had some issues (like
ctx->prog.dirty not getting reset at the end of the batch). It also
required some special hacks to avoid resetting dirty state on binning
pass. So just move it all into ctx->dirty (leaving some free bits
for future shader stages), and make FD_DIRTY_PROG just be the union
of all FD_SHADER_DIRTY_*.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ofc won't catch *all* faults, but at least helpful for catching offsets
which are completely bogus.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Now that the opc's encode the instruction category (making them unique)
we no longer need to check the category in addition to the opc.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
The instruction encoding allows for more registers, but at least on
a3xx/a4xx they don't actually exist.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Helps reduce register pressure and instruction counts for immediates
that would otherwise require a mov into gpr.
total instructions in shared programs: 4455332 -> 4369297 (-1.93%)
total dwords in shared programs: 8807872 -> 8614432 (-2.20%)
total full registers used in shared programs: 263062 -> 250846 (-4.64%)
total half registers used in shader programs: 9845 -> 9845 (0.00%)
total const registers used in shared programs: 1029735 -> 1466993 (42.46%)
half full const instr dwords
helped 0 10415 0 17861 5912
hurt 0 1157 21458 947 33
Signed-off-by: Rob Clark <robclark@freedesktop.org>
When computing the offset in the uniform storage table, take into account
the size multiplier so double precision matrices are handled correctly.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Split 32-bit and 64-bit fmod lowering as the drivers might need to
lower them separately inside NIR depending on the HW support.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
There are rounding errors with the division in i965 that affect
the mod(x,y) result when x = N * y. Instead of returning '0' it
was returning 'y'.
This lowering pass fixes those cases.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
GEN_LT has a straightforward implementation on which we can build the
GEN_GE and GEN_LE macros.
Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
For opcodes that changed meaning on different generations, we store a
pointer to a secondary table and the table's size in a tagged union in
place of the mnemonic and number of sources.
Acked-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
The previous commit replaced direct uses of opcode_descs with calls to
the wrapper function, which should be the only method of accessing
opcode_descs's data. As a result gen_from_devinfo() can also be made
static.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
I merged opcode_desc into inst_info (instead of the other way around)
because inst_info was sorted by opcode number.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Drop the uses of 'enum gen' to a plain int, so that we don't have to
expose the bitfield definitions and GEN_GE/GEN_LE macros to other users
of brw_eu.h. As a result, s/.gen/.gens/ to avoid confusion with
devinfo->gen.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
The function takes a device info struct as argument in addition to the
opcode number in order to disambiguate between multiple opcode_desc
entries for different instructions with the same opcode number.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> [v1]
[v2] mattst88: Put brw_opcode_desc() in brw_eu.c instead of moving it
there in a later patch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v2]
[v3] mattst88: Return NULL if opcode >= ARRAY_SIZE(opcode_descs)
Reviewed-by: Matt Turner <mattst88@gmail.com>
This is not strictly required for the following changes because none
of the three-source opcodes we support at the moment in the compiler
back-end has been removed or redefined, but that's likely to change in
the future. In any case having hardware instructions specified as a
pair of hardware device and opcode number explicitly in all cases will
simplify the opcode look-up interface introduced in a subsequent
commit, since the opcode number alone is in general ambiguous.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
A future series will implement support for an instruction that happens
to have the same opcode number as another instruction we support
already on a disjoint set of hardware generations. In order to
disambiguate which instruction it is brw_instruction_name() will need
some way to find out which device we are generating code for.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Unlike most shader stages, the Hull Shader hardware makes us explicitly
tell it how many threads to dispatch and manually configure the channel
mask. One perk of this is that we have a lot of flexibility - we can
run it in either SIMD4x2 or SIMD8 mode.
Treating it as SIMD8 means that shaders with 8 or fewer output vertices
(which is overwhemingly the common case) can be handled by a single
thread. This has several intriguing properties:
- Accessing input arrays with gl_InvocationID as the index is a simple
SIMD8 URB read with g1 as the header. No indirect addressing required.
- Barriers are no-ops.
- We could potentially do output shadowing to combine writes, as the
concurrency concerns are gone. (We don't do this yet, though.)
v2: Drop first_non_payload_grf change, as it was always adding 0
(caught by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
I'm about to implement a scalar TCS backend, and I'd rather not
duplicate all of this code there.
One change is that we now write the tessellation levels from all
TCS threads, rather than just the first. This is pretty harmless,
and was easier. The IF/ENDIF needed for that are gone; otherwise
the generated code is basically identical.
I chose to emit load/store intrinsics directly because it was easier.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
If we fail to create a context in the VMware driver we call this function
unconditionally to free a bunch of bit vectors. Instead of asserting on
a null pointer, just no-op.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
If, for example, we previously had 2 sampler states bound and now we
are binding one, we'd leave the second sampler state unchanged.
This change nulls-out the second sampler state in this situation.
We're already doing the same thing for sampler views.
This silences an occasional warning issued by the VMware driver when
the number of sampler views and sampler states disagreed.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
This silences some warnings when we try to sample from surfaces that were
created for drawing, such as when blitting from one of the framebuffer
surfaces. We were already doing the opposite situation (adding a bind
flag for rendering to surfaces declared as texture sources).
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Like cube maps, we need to convert the z information to a layer index.
Also rename the *_face vars to *_face_layer to make things a little more
understandable.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
metric-issue_slot_utilization and metric-branch_efficiency are already
computed as percentages.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
This will allow to use percentages for some metrics because the Gallium
HUD doesn't allow to display floating point numbers and 0 is printed
instead.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
This is most likely a copy-paste error when I reworked this area few
weeks ago. For SM20, metric-issue_slots is equal to inst_issued because
there is only one pipeline, so the metric is not exposed there.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reported-by: Karol Herbst <nouveau@karolherbst.de>
This fixes two of the cases in
GL43-CTS.shader_subroutine.subroutines_not_allowed_as_variables_constructors_and_argument_or_return_types
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
resource just appears in GLSL 4.20 without any fanfare.
Fixes GL43-CTX.CommonBugs.CommonBug_ReservedNames
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
