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Author SHA1 Message Date
José Roberto de Souza
da63c54db5 intel/perf: Remove i915_drm.h includes from common code 
Only place that still has i915_drm.h includes in common code is
intel_perf_query.c.

This are the last i915_drm.h includes in headers in common code \o/.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29312>
 2024-06-29 01:17:37 +00:00
José Roberto de Souza
00c6b09812 tool/pps: Add Xe KMD support 
This is the same config as intel.cfg only changing:

data_sources {
  config {
    name: "gpu.counters.i915"
    gpu_counter_config {
      counter_period_ns: 100000
    }
  }
}

to:

data_sources {
  config {
    name: "gpu.counters.xe"
    gpu_counter_config {
      counter_period_ns: 100000
    }
  }
}

Otherwise pps would not accept due to different KMD names.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29312>
 2024-06-29 01:17:37 +00:00
José Roberto de Souza
c2fd848002 intel/perf: Refactor and add Xe KMD support to change stream metrics id 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29312>
 2024-06-29 01:17:37 +00:00
José Roberto de Souza
b22899b494 intel/perf: Refactor and add Xe KMD support to enable and disable perf stream 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29312>
 2024-06-29 01:17:37 +00:00
José Roberto de Souza
981090f173 intel/perf: Add Xe KMD perf stream open function 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29312>
 2024-06-29 01:17:37 +00:00
José Roberto de Souza
6258c84375 intel/perf: Refactor and add Xe KMD support to add and remove configs 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29312>
 2024-06-29 01:17:37 +00:00
José Roberto de Souza
0e68d7a735 intel/perf: Replace i915_perf_version and i915_query_supported by a feature bitmask 
Replacing the i915_perf_version that is i915 specific by a feature
mask makes easier to support Xe KMD.
Also this allow us to group a bool and a int into a single enum(int).

No changes in behavior is expected here.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29312>
 2024-06-29 01:17:37 +00:00
José Roberto de Souza
a56b085661 intel/perf: Add function to check if OA/perf is supported by Xe KMD 
This is a uAPI added after initial Xe KMD upstreaming so not supported
by every version, also by default it requires high privilege
permissions so it check if current applications has it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29312>
 2024-06-29 01:17:37 +00:00
José Roberto de Souza
f0c62b6438 intel/perf: Implement function that returns OA format for Xe KMD 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29312>
 2024-06-29 01:17:37 +00:00
José Roberto de Souza
bdeeaaff59 intel: Sync xe_drm.h 
Sync xe_drm.h with 406d058dc323 ("drm/xe/oa/uapi: Allow preemption to be disabled on the stream exec queue").
Patch available in https://gitlab.freedesktop.org/drm/kernel/-/blob/drm-next/.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29312>
 2024-06-29 01:17:37 +00:00
Sushma Venkatesh Reddy
d52dd5a9e9 anv/drirc: add option to provide low latency hint 
GuC offers a mechanism for KMD/UMD to provide workload hints and one of
that strategy is low latency hint. We can utilize this hint when the
workload is more latency sensitive like compute usecases.

Signed-off-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28282>
 2024-06-28 21:45:59 +00:00
Jesse Natalie
d0151df322 mesa: Add ASSERTED to assert-only local variable 
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29970>
 2024-06-28 20:44:36 +00:00
Jesse Natalie
13d11ab442 zink: Add ASSERTED to assert-only local variable 
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29970>
 2024-06-28 20:44:36 +00:00
Jesse Natalie
c2b53d7bd0 nir: Remove assert-only variable by inlining its single use 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29970>
 2024-06-28 20:44:36 +00:00
Alyssa Rosenzweig
30db807f79 nir/algebraic: explicitly suffix constants 
Make our intentions super duper clear.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29952>
 2024-06-28 19:53:36 +00:00
Alyssa Rosenzweig
270446ee21 nir: fix miscompiles with rules with INT32_MIN 
812b3415 added rules for upcasts with comparisons with a variety of
types. The float & unsigned rules should be ok, but the signed integer rules are
unsound as currently implemented. This can cause end-to-end miscompiles.

I originally hit this issue while debugging a large real world OpenCL kernel. I
found the bug symptoms changed when disabling loop unrolling, which tipped me
off to a compiler bug. I've reduced it to a minimal test case. Imagine my
surprise when I find out the NIR my backend ingested was already constant folded
to be wrong.

In the minimal test case, during optimization we have NIR:

        32     %6 = ....
        64     %9 = i2i64 %6
        64    %44 = load_const (0x0000000000000001)
        1     %45 = ilt %9, %44 (0x1)

This is a simple check (int64_t)%6 < 1.

nir_opt_algebraic turns this into:

        32     %6 = ...
        64     %9 = i2i64 %6
        64    %44 = load_const (0x0000000000000001)
        64    %55 = load_const (0x0000000080000000 = 2147483648)
        1     %56 = ilt %55 (0x80000000), %44 (0x1)
        64    %57 = load_const (0x000000007fffffff = 2147483647)
        1     %58 = ilt %57 (0x7fffffff), %44 (0x1)
        32    %59 = i2i32 %44 (0x1)
        1     %60 = ilt %6, %59
        1     %61 = ior %58, %60
        1     %62 = iand %56, %61

This pile of math constant-folds to an unconditional "false"!  The problem is
%56. At first glance, INT32_MIN < 1 is true so %56 should be true. Indeed, it
should. But here's the kicker: both constants are 64-bit here, so the ilt
operation is a 64-bit comparison -- that left-hand side is INT32_MIN
zero-extended to 64-bit for the signed comparison at 64-bit. So in fact, it
evaluates to false, causing the whole expression to go false.  If we're going to
do a 64-bit comparison for %56, then we need to sign-extend the bound.  So we'll
just adjust the Python and be on our way, right?

Unfortunately the issue is deeper. According to the comment in the generated
nir_opt_algebraic.c file, the guilty algebraic rule is:

   ('ilt', ('i2i64', 'a@32'), '#b') =>
   ('iand', ('ilt', -2147483648, 'b'), ('ior', ('ilt', 2147483647, 'b'), ('ilt', 'a', ('i2i32', 'b'))))

From a Python perspective? That rule is correct. -2147483648 < 1 is a true
statement. Adjusting the Python rule is not the appropriate solution here, since
the issue is more fundamental and might affect other rules.  The real problem is
the translation of that Python replacement tree into C, incorrectly
zero-extending -2147483648 into 0x0000000080000000 instead of sign-extending to
0xffffffff80000000.

Crawling down the rabbit hole of the generated algebraic file, we see the
constant encoded as:

   { .constant = {
      { nir_search_value_constant, 64 },
      nir_type_int, { -0x80000000 /* -2147483648 */ },
   } },

NIR correctly translates the negative constant to a C level negate operation of
its absolute value. This maps to the correct sign-extension...

...for all constants except for INT_MIN. Because that constant lacks a ULL
suffix, it is a 32-bit integer. And for this integer (only), negating it hits
signed integer overflow (UB!) and then we end up with an effective
zero-extension when going to 64-bit.

This patch fixes the end-to-end miscompile.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Closes: #11402
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29952>
 2024-06-28 19:53:36 +00:00
Maaz Mombasawala
8b756a0d0e svga: Replace shared surface flag and simplify surface creation 
The shared flag vmw_svga_winsys_surface was used to create shareable surfaces
and these surfaces are not discarded.
Since all surfaces created right now are shareable, there is no need for this
flag except to mark surfaces which should not be discarded. Renaming it to
nodiscard accordingly.
This also simplifies surface creation.

Signed-off-by: Maaz Mombasawala <maaz.mombasawala@broadcom.com>
Reviewed-by: Martin Krastev <martin.krastev@broadcom.com>
Reviewed-by: Ian Forbes <ian.forbes@broadcom.com>
Reviewed-by: Jose Fonseca <jose.fonseca@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29948>
 2024-06-28 19:41:02 +00:00
Neha Bhende
8b8f347e4b svga: Retrieve stride info from hwtnl->cmd.vdecl for swtnl draws 
This fixes spec@!opengl 1.0@gl-1.0-polygon-line-aa
spec@!opengl 1.1@clipflat and multiple piglit tests
failures on VGPU9 device

Fixes: 76725452 ("gallium: move vertex stride to CSO")

Reviewed-by: Brian Paul <brian.paul@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29947>
 2024-06-28 19:24:46 +00:00
Rémi Bernon
f9a15b37ef zink: Add VKAPI_PTR specifier to generated stub functions. 
Same as 8d210ae232 but for when NDEBUG
isn't defined.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29863>
 2024-06-28 18:15:34 +00:00
Mike Blumenkrantz
6466a977e4 zink: add a driver workaround to disable 2D_VIEW_COMPATIBLE+sparse 
this fixes a lot of stuff on intel and hopefully never hits any corner
case app use

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29197>
 2024-06-28 17:44:00 +00:00
Jesse Natalie
e8ab5e4320 d3d12: Use GetResourceAllocationInfo instead of GetCopyableFootprints for residency sizes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29967>
 2024-06-28 17:21:52 +00:00
José Expósito
1ef3b38ff8 llvmpipe: Init eglQueryDmaBufModifiersEXT num_modifiers 
Initialize the number of modifiers when `max` is 0 as documented [1]:

  If <max_formats> is 0, no formats are returned, but the total number
  of formats is returned in <num_formats>, and no error is generated.

[1] https://registry.khronos.org/EGL/extensions/EXT/EGL_EXT_image_dma_buf_import_modifiers.txt

Fixes: d74ea2c117 ("llvmpipe: Implement dmabuf handling")
Reported-by: Michal Odehnal <modehnal@redhat.com>
Tested-by: Michal Odehnal <modehnal@redhat.com>
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Signed-off-by: José Expósito <jexposit@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29941>
 2024-06-28 16:57:26 +00:00
Caio Oliveira
6dc7f65a39 anv: Use brw_nir_lower_cs_intrinsics for lowering Mesh/Task LocalID 
Stop using the option in the generic pass
nir_lower_compute_system_values and use the same code as brw uses for
compute instead.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29828>
 2024-06-28 16:30:38 +00:00
Caio Oliveira
d89bfb1ff7 intel/brw: Reorganize lowering of LocalID/Index to handle Mesh/Task 
Reorganize the code to make clearer all the lowering cases:

(a) Single invocation workgroup.  Index and IDs are all zero.
(b) Local ID provided by hardware.
(c) Local Index provided by the hardware.  Depending on the case this
    might not be the final local index, e.g. heuristics for tile.
(d) Neither provided by the hardware.

Case (c) is new and supported by Mesh/Task shaders.  At the moment the
nir_lower_compute_system_values handle lowering of LocalID for
Task/Mesh, but a later patch will flip that on ANV.

This will make the Task/Mesh use the same lowering as Compute shaders.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29828>
 2024-06-28 16:30:38 +00:00
Juan A. Suarez Romero
f0b0a71a9b ci: disable Igalia farm 
We have some network issues which prevents the hosts do their job

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29965>
 2024-06-28 16:27:17 +00:00
Connor Abbott
81fd13913a freedreno: Fix RBBM_NC_MODE_CNTL variants 
It exists on a6xx too, as made clear by kgsl.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29961>
 2024-06-28 15:09:04 +00:00
Samuel Pitoiset
cc48e12431 radv: suspend user conditional rendering when DGC has task shaders 
Otherwise the DGC ACE IB would be uninitialized and it would hang.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29954>
 2024-06-28 14:35:22 +00:00
David Rosca
49eda4d742 frontends/va: Don't require exact match for packed headers 
Apparently it's valid to create config with any combination of supported
packed headers.

Fixes libva-utils tests:
 GetCreateConfig/VAAPIGetCreateConfig.CreateConfigWithAttributes/235, where GetParam() = (32:VAProfileAV1Profile0, 6:VAEntrypointEncSlice)
 GetCreateConfig/VAAPIGetCreateConfig.CreateConfigPackedHeaders/235, where GetParam() = (32:VAProfileAV1Profile0, 6:VAEntrypointEncSlice)
 QuerySurfaces/VAAPIQuerySurfaces.QuerySurfacesWithConfigAttribs/235, where GetParam() = (32:VAProfileAV1Profile0, 6:VAEntrypointEncSlice)
 CreateSurfaces/VAAPICreateSurfaces.CreateSurfacesWithConfigAttribs/3995, where GetParam() = (32:VAProfileAV1Profile0, 6:VAEntrypointEncSlice, 16x16)

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29934>
 2024-06-28 14:19:22 +00:00
David Rosca
a3f35964ba gallium/vl: Init shaders on first use 
It takes significant amount of time at va context creation, and most
of the time the postproc pipelines are not used anyway.
This reduces total time it takes to run all libva-utils tests on my machine
from 38s to 28s.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29936>
 2024-06-28 13:34:35 +00:00
Luc Ma
6f1dd9a2aa gallium: inline trivial needs_pack() 
No functional change.

Signed-off-by: Luc Ma <luc@sietium.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29833>
 2024-06-28 11:22:23 +00:00
Luc Ma
cde1a1d5c2 gallium: properly propagate the usage of resource 
In case that some drivers might make decision depending on it,
it is better to tell drivers about usage of resource just like
in `blit_to_staging()` and `st_TexSubImage()` etc before going
to blit.

Signed-off-by: Luc Ma <luc@sietium.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29833>
 2024-06-28 11:22:23 +00:00
Konstantin Seurer
9ae1c5dce3 radv: Refactor radv_(dst|src)_access_flush 
A few ifs should be faster and more readable than looping over every set
bit.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
41619da397 radv: Handle AS access bits like shader storage access bits 
Acceleration structures are accessed directly from shaders or via
PKT3_WRITE_DATA.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
ca96abe1cb radv: Remove write access handling from radv_dst_access_flush 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
3eefd0b040 radv: Remove handling for expanded access flags 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
135348a3c3 radv: Remove no-op access flag handling 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
3acab3dfff radv: Use vk_expand_(src|dst)_access_flags2 
Simplifies access flags handling since the driver doesn't have to worry
about VK_ACCESS_2_MEMORY_READ_BIT and friends.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
b0fa138c86 vulkan: Add vk_expand_(dst|src)_access_flags2 
Those helpers do not filter out dead access bits to keep synchronization
conservative.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
7b3cdacf7f vulkan: Handle group stages in vk_.*_access2_for_pipeline_stage_flags2 
Avoids calling vk_expand_.*_stage_flags2.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Eric Engestrom
76db69047f panfrost/ci: split gl & vk jobs rules 
No need to run all the gl jobs on vk changes, and vice-versa.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29942>
 2024-06-28 08:19:07 +00:00
Eric Engestrom
cdc0e60df5 panfrost/ci: drop duplicate job rules 
It's overwritten by the `.panfrost-bifrost-manual-rules` 3 lines below.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29942>
 2024-06-28 08:19:07 +00:00
Samuel Pitoiset
88864b707a radv: enable task shaders support with NV DGC 
No games are using task shaders with DGC at the moment but this is
supposed to work.

This fixes test_amplification_shader_execute_indirect from vkd3d.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
e6aee84265 radv: fix a synchronization issue with non-preprocessed DGC with task shader 
We need to make sure that the DGC ACE IB will wait for the DGC
prepare shader before the execution starts. When DGC is preprocessed
the synchronization is already correct.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
74713469e1 radv: disable conditional rendering with DGC and task shaders 
When the DGC prepare shader is conditionally executed on the graphics
queue, the generated IBs might be uninitialized. It's fine for the
DGC GFX IB because the INDIRECT_PACKET would also be conditionally
skipped but it's not possible to do that for the DGC ACE IB
(ie. no IB2 on compute).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
fec2385301 radv: emit push constant for task shaders with DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
1ffb420edd radv: adjust the base upload offset when DGC uses task shaders 
The upload space is after the DGC ACE IB.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
f55d4f2f09 radv: reserve space for push constants in the DGC ACE IB 
The upload space will be shared for both IBs when push constants need
to be allocated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
8d321421c7 radv: rework emitting push constants with DGC 
Using a push constant stages mask to emit them in the DGC ACE IB for
task shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
f6150edbb3 radv: split allocating and emitting push constants with DGC 
This will allow us to emit push constants for task shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
1f7bdcfa8d radv: add a helper that determines if DGC uses task shaders 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00