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Author SHA1 Message Date
Qiang Yu
acde71c015 radeonsi: use nir_print_xfb_info to replace si_dump_streamout 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
 2023-01-18 05:30:13 +00:00
Qiang Yu
def3f700bc radeonsi: lower nir streamout intrinsics in abi 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
 2023-01-18 05:30:13 +00:00
Qiang Yu
743fbc4bb0 radeonsi: implement nir_load_ring_gs2vs_offset_amd 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
 2023-01-18 05:30:13 +00:00
Qiang Yu
16cf743f2d radeonsi: implement nir_load_ring_gsvs_amd 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
 2023-01-18 05:30:13 +00:00
Emma Anholt
8aff228127 ci: Enable building the testing drivers with perfetto. 
We've talked about being able to capture perfetto traces from CI jobs for
a while, and this would be a step toward that.  Mostly it's that we
occasionally break the perfetto build, so let's make sure we don't do
that.

Acked-by: Rob Clark <robdclark@chromium.org>
Acked-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>
 2023-01-18 05:04:46 +00:00
Emma Anholt
64455dc32b freedreno/pps: Fix a signed/unsigned complaint. 
../src/freedreno/ds/fd_pps_driver.cc:656:44: error: comparison of integer expressions of different signedness: '__gnu_cxx::__alloc_traits<std::allocator<int>, int>::value_type' {aka 'int'} and 'const unsigned int' [-Werror=sign-compare]
  656 |             assert(d->assigned_counters[i] < g->num_counters);
cc1plus: all warnings being treated as errors

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>
 2023-01-18 05:04:46 +00:00
Emma Anholt
302858c48c ci/freedreno: Add glx-swap-event-async as a flake. 
It's only happened a few times in the last year (used to be more popular),
but it just took out a merge.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>
 2023-01-18 05:04:46 +00:00
Emma Anholt
327f736627 freedreno: Skip CPU/GPU timestamp sync when not supported. 
Fixes immediate segfaults in perfetto-enabled builds on pre-a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>
 2023-01-18 05:04:46 +00:00
Emma Anholt
79bbfb3168 ci/zink: Add more blit conversion xfails for a618. 
Popular cases in this group recently:

      1 dEQP-GLES3.functional.fbo.blit.conversion.r16ui_to_r16ui
      1 dEQP-GLES3.functional.fbo.blit.conversion.r16ui_to_rgb10_a2ui
      1 dEQP-GLES3.functional.fbo.blit.conversion.rgb5_a1_to_rgb5_a1
      3 dEQP-GLES3.functional.fbo.blit.conversion.rgba4_to_r32f
      4 dEQP-GLES3.functional.fbo.blit.conversion.rgb565_to_rgba8
      5 dEQP-GLES3.functional.fbo.blit.conversion.rgba4_to_rg16f

There's pretty clearly something common with blitting from 16-bit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>
 2023-01-18 04:43:59 +00:00
Emma Anholt
c4c94e8aed ci/iris: Generalize the 8888_pbuffer EGL known flakes and share with GLK. 
It seems to be this whole group of tests, on both boards that run EGL
tests by default (aml-y is manual-only).  Make them a regex until someone
comes up with a fix.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>
 2023-01-18 04:43:59 +00:00
Emma Anholt
6dc90009a5 ci/iris: Add known flakes for skqp. 
We've had a lot more jobs run since I landed the CI, and these seem to be
the common flakes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>
 2023-01-18 04:43:59 +00:00
Emma Anholt
c34b539e17 ci/llvmpipe: Drop dEQP-EGL.functional.sharing.*.link.7 flakes. 
These appear to have been resolved by !20458 -- went from typically
multiple per day to none since then.  The link.19 fails to seem to still
happen, though.

Closes: #7759
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>
 2023-01-18 04:43:59 +00:00
Jason Ekstrand
d292cb82b8 gallium,util: Pull u_indices and u_primconvert back into gallium 
This was moved in !13741 but doing so created a link-time dependency
between util and gallium which causes problems for Vulkan drivers.
Meanwhile, having mesa/main depend on gallium is fine now that we don't
have any classic drivers.  It's a bit circular but should be harmless.

Fixes: 97ba2f2fd4 ("move util/indices to core util")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8098
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20734>
 2023-01-18 03:53:30 +00:00
Ikshwaku Chauhan
fe3b467eb9 radeonsi: Fix distortion for yuv422 format for GFX10. 
For yuv422 format camera show blur output for GFX10.

Signed-off-by: Ikshwaku Chauhan <ikshwaku.chauhan@amd.com>
Reviewed-by: Marek Olšák marek.olsak@amd.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20610>
 2023-01-18 01:44:15 +00:00
Corentin Noël
5348704820 ci/venus: Remove failure now passing 
It has been fixed either in the CTS or in llvmpipe itself but this now passes when running
in CI.

We haven't seen it in CI yet as we are only running a subset of the Vulkan CTS.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20743>
 2023-01-17 23:56:45 +00:00
Mike Blumenkrantz
dc8c9d2056 zink: prune old swapchains on present 
pruning old swapchains is challenging because there's no way to definitively
know when to destroy them without VK_EXT_swapchain_maintenance1 which isn't
supported yet

initially, I handled it by only pruning on shutdown and whenever a new swapchain
was created since those are both safe points, but this leads to scenarios where
a dead swapchain can exist for the entire lifetime of an application
if the swapinterval is changed

to avoid such ballooning, check whether the current swapchain has ever presented
on each present queue and then prune based on this

fixes #7529

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20588>
 2023-01-17 23:21:58 +00:00
Emma Anholt
6b0db6bf8b dri2: Fix exposing robustness with swkms. 
In the original change I noticed that missing robustness on swkms seemed
to be an oversight, since it was enabled on sw-non-kms, so I exposed the
ext based on the underlying pipe query.  However it turns out that there
is a dri_screen flag for allowing robust contexts that exists to do error
checking for GLX, which was under an !swkms check.  So we would expose the
ext, but then throw an error if you tried to create one.

Fixes: e6285ea55f ("egl: Replace the robustness DRI2 ext check with a pipe cap query.")
Closes: #8066
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20679>
 2023-01-17 21:19:18 +00:00
Jesse Natalie
ca8c8f2fc1 dzn: Remove cmdbuf query 'wait' list 
From the Vulkan spec, the WAIT flag on vkCmdCopyQueryPoolResults only
serves to increase the first synchronization scope to include query end
commands, but either way, the synchronization scope only includes
commands that occur earlier in submission order. In other words, we
don't need to enforce queue ordering, a pipeline barrier is all that's
needed.

Fixes deadlocks in the timestamp.misc_tests.two_cmd_buffers_primary test.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
 2023-01-17 20:17:42 +00:00
Jesse Natalie
261102bd9c dzn: Fix format support checks for storage/uniform texel buffers 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
 2023-01-17 20:17:42 +00:00
Jesse Natalie
0069ac9e6e dzn: Disable depth when the rasterizer is disabled due to no position output 
D3D considers the rasterizer enabled if there's a pixel shader *or* if
depth is enabled, since you can do depth-only rendering. After parsing
shaders, if we find that there was supposed to be a pixel shader, but
we removed it because there was no output position, disable depth too.

Also, store this info in the cache, since we might not even load the
nir shaders if we'd seen this pipeline before.

Fixes dEQP-VK.synchronization.internally_synchronized_objects.pipeline_cache_graphics

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
 2023-01-17 20:17:42 +00:00
Jesse Natalie
682605a99b dzn: Add a zeroed zsa state when depth or raster is disabled 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
 2023-01-17 20:17:42 +00:00
Jesse Natalie
25d460a818 dzn: Always align cached pipeline header size to input element align 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
 2023-01-17 20:17:42 +00:00
Jesse Natalie
4565490b71 dzn: Support unnormalized coordinate samplers 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
 2023-01-17 20:17:42 +00:00
Jesse Natalie
552ab9c2f7 dzn: Support root signature 1.2 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
 2023-01-17 20:17:42 +00:00
Jesse Natalie
1e0adac84a dzn: Define a symbol that was present in older D3D headers 
D3D12_BARRIER_SYNC_INPUT_ASSEMBLER was renamed to D3D12_BARRIER_SYNC_INDEX_INPUT,
so conditionally define the old name based on the version of the headers that are
being used.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
 2023-01-17 20:17:42 +00:00
EmperorPenguin18
3eb33ec9e9 v3d: expose more drm formats with SAND128 modifier 
Adds four more PIPE_FORMATs that expose BROADCOM_SAND128. This allows mpv
to do hardware decoding on the Raspberry Pi 4.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7944
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20510>
 2023-01-17 19:57:28 +00:00
Rob Clark
aac66fe039 freedreno/a6xx: Rework barrier handling 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
 2023-01-17 19:32:13 +00:00
Rob Clark
63e889516d freedreno: Don't re-install a flushed batch 
The compute path does this save/restore dance with the current batch, so
various things called to emit state can assume ctx->batch is the current
thing.  But during resource tracking, which could have flushed what was
previously the current batch.  Fixes a problem that surfaces in the next
patch when we stop just flushing batches for all the barriers.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
 2023-01-17 19:32:13 +00:00
Rob Clark
aa9b62cad3 freedreno/a6xx: Workaround for no pos/psize 
The hw seems unhappy if there are zero outputs from the last geometry
stage.  So add a dummy varying as a workaround.  Turnip got a similar
workaround in commit d6d75fcd91 ("tu: Fix hangs for DS with no output")

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
 2023-01-17 19:32:13 +00:00
Rob Clark
e41d19a711 freedreno: Fix tracking of enabled SSBOs 
Clearing all of the modified bits an relying on OR'ing the needed bits
back in the loop below doesn't quite work out, Because of early continue
if the SSBO has not changed.

Fixes: 0ed053f03d ("freedreno: simplify fd_set_shader_buffers(..)")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
 2023-01-17 19:32:13 +00:00
Rob Clark
ca2011d11c freedreno/drm: Remove assert 
We can hit this scenario if there is a GPU hang before the userspace
fence writeback happens.  Since we have asserts enabled in CI, just
remove this assert.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
 2023-01-17 19:32:13 +00:00
Gert Wollny
adee0e7e53 r600/sfn: Do a bit of cleanup with the secondary read port validation 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20739>
 2023-01-17 19:19:01 +00:00
Gert Wollny
ca5bbff558 r600/sfn: Fix readport check 
We have to take multi-slot instructions into account, and we don't fail
when there are still possible bank swizzle values to be checked.

For clarity also rename the bank swizzle iterator iterator.

Fixes: 79ca456b48
   r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20739>
 2023-01-17 19:19:01 +00:00
Rhys Perry
42d51ef2bb radv/gfx11: expose shaderBufferFloat32AtomicAdd 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
 2023-01-17 17:39:15 +00:00
Rhys Perry
7dd16791ca radv: load ssbo_atomic_fadd descriptor 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
 2023-01-17 17:39:15 +00:00
Rhys Perry
068c84f275 aco: add support for fp32 addition atomics 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
 2023-01-17 17:39:15 +00:00
Rhys Perry
ea1ac3901a ac/llvm: add support for fp32 addition atomics 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
 2023-01-17 17:39:15 +00:00
José Roberto de Souza
e879b28994 anv: Move anv_device_check_status() code to i915/anv_device.c 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
 2023-01-17 17:10:18 +00:00
José Roberto de Souza
94af444490 anv: Split i915 code from anv_batch_chain.c 
There is no change in behavior here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
 2023-01-17 17:10:18 +00:00
José Roberto de Souza
94ca73b356 anv: Export anv_exec_batch_debug() and chain_command_buffers() 
This functions will be used by i915 and Xe KMD.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
 2023-01-17 17:10:18 +00:00
José Roberto de Souza
80c89c4606 anv: Start to move i915 specific code from anv_device to i915/anv_device 
More code re-organization to separate i915_drm.h specific code from
the rest.

No behavior changes here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
 2023-01-17 17:10:18 +00:00
Gert Wollny
8084b412ca virgl: drop the separable flag for cases that can't be handled 
The host can't assign more than 32 locations explicitly, and we
exhaust this already when we handle patches and generics. So
drop the separable flag in cases when we have other IO that
uses generated names that will have to be matched by name.

v2: skip tests for VS input and FS outputs

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20738>
 2023-01-17 16:58:52 +00:00
Rob Clark
aa7c83786d freedreno/ci: Add an a618 flake 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
 2023-01-17 16:33:29 +00:00
Rob Clark
a7a46556ec Revert "freedreno/ci: Switch a630 jobs over to manual" 
This reverts commit 0cc3701338.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
 2023-01-17 16:33:29 +00:00
Rob Clark
23e6d0ce79 Revert "freedreno/ci: Switch also performance a630 job to manual" 
This reverts commit 3be7a28b24.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
 2023-01-17 16:33:29 +00:00
Lionel Landwerlin
f9115b6d51 intel: use a shared UUID with other drivers 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20408>
 2023-01-17 17:36:07 +02:00
Tapani Pälli
53de48f1c4 intel/compiler: add cpp_std=c++17 when building tests 
Otherwise build fails:

"../src/intel/compiler/brw_private.h:40:4: note:
 ‘std::variant’ is only available from C++17 onwards"

Fixes: 6c194ddd18 ("intel/compiler: Prepare SIMD selection helpers to handle different prog_datas")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20725>
 2023-01-17 13:58:03 +00:00
Gert Wollny
d59e5aa08f virgl: Request setting the atomic offset in the range_base 
With that NTT can encode the array base of atomic arrays separately
so that the host driver can address the arrays correctly.

Fixes GL-CTS: KHR-Single-GL43.arrays_of_arrays_gl.AtomicUsage

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00
Gert Wollny
994cf0e995 virgl: lower image variable offsets into the intrinsic range_base value 
With that we get the correct base offset when accessing image arrays.
This is required if there a various images with different access
specifiers, because only with the correct base offset the host driver is
able to pick the right array.

Fixes GL-CTS: KHR-GL43.shading_language_420pack.binding_image_array

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00
Gert Wollny
7380656a8c ntt: Make use of the range_base offset when translating atomics in NTT 
v2: Unconditionally add teh range base, it is properly initialized.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00