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Author SHA1 Message Date
Vasily Khoruzhick
24be011901 lima: wire up MSAA 4x support 
Utgard supports MSAA 4x, so wire it up.

RSW bits were already REd by Luc, the only remaining part was storing
non-resolved buffers, reloading them (including for depth/stencil) and
doing MSAA resolve.

To store non-resolved buffer we need to set mrt_pitch and mrt_bits
registers in WB, and to resolve non-resolved buffer we need to reload
it into individual samples and then write out with mrt_bits = 0, it's
now done by lima blitter.

We also need to do resolve on transfer_map() of multi-sampled buffers,
so utilize u_transfer_helper for that.

As a side fix, it turns out that our wb_reg definition wasn't correct,
'zero' isn't always zero, it's set if we need to swap channels, and
it goes before mrt_bits. mrt_bits actually enables multiple MRTs,
so this commit renames 'zero' to 'flags' and changes its position.

If mrt_bits == 0 and MSAA is enabled, GPU does resolve
in place, to expose this functionality we set PIPE_CAP_SURFACE_SAMPLE_COUNT.

Fixes dEQP-GLES2.functional.multisample.*

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13963>
 2022-06-28 00:00:35 +00:00
Emma Anholt
f93bee19d9 ci/turnip: Trim the a630 VK run a bit. 
We have a lot of spilling coverage in a618 pre-merge, don't do it all (~2
minutes) here.  Also, force-gmem touch testing should probably test less than
the default run does!

This should help make up for having added the tu-zink run.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17125>
 2022-06-27 22:38:54 +00:00
Emma Anholt
523ed9521b ci/turnip: Test traces on turnip using zink. 
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17125>
 2022-06-27 22:38:54 +00:00
Emma Anholt
8e53194f44 ci/freedreno: Add vulkan+gl integration testing in piglit. 
The libvulkan-dev was needed for building zink, which ended up turning on
the vulkan tests in piglit.  Split them out here.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17125>
 2022-06-27 22:38:54 +00:00
Emma Anholt
9090bb1fbd ci/traces: Drop ZINK_USE_LAVAPIPE ICD override. 
Not set in the tree any more.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17125>
 2022-06-27 22:38:54 +00:00
Emma Anholt
83709ac3cf ci/traces: GC unused code for DXVK trace replay. 
I haven't found any use of it since it was introduced, and it got in the
way of zink trace testing.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17125>
 2022-06-27 22:38:53 +00:00
Mike Blumenkrantz
67bbe79d35 lavapipe: always set point_tri_clip 
this invokes GLES-compatible point clipping, which is more consistent
with vulkan expectations and fixes a number of zink tests

Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17259>
 2022-06-27 21:36:44 +00:00
Alyssa Rosenzweig
f18492faa9 lima,panfrost: Do not ralloc contexts against the screen 
ralloc is not thread-safe. While a given context can only be accessed from a
single thread at once, multiple contexts can be created against the same screen
at once. The ralloc allocations against the shared screens will race. Depending
on the result of the race, the same block of memory can be returned as the two
new contexts in two different threads, causing a use-after-free when the context
is freed later.

We free the context explicitly when it's destroyed anyway. If screens are
getting destroyed without the contexts getting destroyed first, that's a state
tracker bug, not a Panfrost one.

This matches what Iris does.

Fixes crash in test_integer_ops.int_math on Panfrost.

Fixes: 0fcf73bc2d ("panfrost: Move to use ralloc for some allocations")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17234>
 2022-06-27 21:21:00 +00:00
Mike Blumenkrantz
a530b90cd3 zink: remove swizzle from fbfetch lowering 
I had this in at one point to fix something, but now it somehow just
breaks fbfetch instead of fixing anything

cc: mesa-stable

fixes:
dEQP-GLES31.functional.blend_equation_advanced*

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17254>
 2022-06-27 20:38:53 +00:00
Adam Jackson
31b04e420b glx/dri: Fix DRI drawable release at MakeCurrent time 
We want to release the drawables of the context we're coming from, but
we were releasing them from the context we're switching to. This is
probably not a big deal normally because both contexts are likely to be
on the same display, which is all that driReleaseDrawables is really
sensitive to. But if the contexts are on different Displays this would
go quite wrong.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17176>
 2022-06-27 20:03:26 +00:00
Jesse Natalie
59944831a7 microsoft/clc: Add a unit test for unused image kernel args 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17246>
 2022-06-27 16:54:27 +00:00
Jesse Natalie
ca23a4af67 microsoft/clc: Remove dead image vars 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17246>
 2022-06-27 16:54:27 +00:00
Jesse Natalie
fd37959680 microsoft/clc: Fix test double free in the case of compilation failure 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17246>
 2022-06-27 16:54:27 +00:00
Jesse Natalie
d69e258e8e microsoft/clc: Enable tests that pass on server 2022 
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17246>
 2022-06-27 16:54:27 +00:00
Jesse Natalie
2dcbe87271 util/disk_cache: Implement disk_cache_get_function_identifier for Windows 
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17208>
 2022-06-27 16:18:32 +00:00
Lionel Landwerlin
9d7d1c0637 intel/clc: enable fp16 & subgroups for GRL 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17253>
 2022-06-27 15:31:49 +00:00
Lionel Landwerlin
cf44282deb clc: add new feature options for intel_clc 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17253>
 2022-06-27 15:31:49 +00:00
Daniel Schürmann
2e895f8b04 radv: vectorize nir_op_fabs 
Totals from 4 (0.00% of 134913) affected shaders: (GFX10.3)
CodeSize: 37868 -> 36576 (-3.41%)
Instrs: 5332 -> 5169 (-3.06%)
Latency: 24452 -> 24174 (-1.14%)
InvThroughput: 9784 -> 9462 (-3.29%)
VClause: 54 -> 50 (-7.41%)
Copies: 520 -> 519 (-0.19%)
PreVGPRs: 266 -> 264 (-0.75%)

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
 2022-06-27 15:07:27 +00:00
Daniel Schürmann
b45a39c44b radv: vectorize nir_op_fdiv & nir_op_flrp & nir_op_ineg 
These instructions are lowered to fmul/isub.
So, prevent scalarization.

Totals from 49 (0.04% of 134913) affected shaders: (GFX10.3)
VGPRs: 2576 -> 2568 (-0.31%)
SpillVGPRs: 1145 -> 1132 (-1.14%); split: -2.10%, +0.96%
CodeSize: 663968 -> 659376 (-0.69%); split: -1.08%, +0.38%
Scratch: 113664 -> 112640 (-0.90%)
Instrs: 110274 -> 109683 (-0.54%); split: -0.81%, +0.27%
Latency: 2904434 -> 2869588 (-1.20%); split: -1.64%, +0.44%
InvThroughput: 1414237 -> 1396600 (-1.25%); split: -1.69%, +0.44%
VClause: 2899 -> 2891 (-0.28%); split: -0.93%, +0.66%
SClause: 1520 -> 1537 (+1.12%); split: -0.07%, +1.18%
Copies: 28829 -> 28662 (-0.58%); split: -1.90%, +1.32%
Branches: 3560 -> 3564 (+0.11%)
PreVGPRs: 2550 -> 2427 (-4.82%)

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
 2022-06-27 15:07:27 +00:00
Daniel Schürmann
def3690447 radv: use callback for nir_lower_to_scalar 
Now uses nir_lower_alu_width.
This avoids scalarization and re-vectorization of 16bit instructions.

Totals from 289 (0.21% of 134913) affected shaders: (GFX10.3)
VGPRs: 12864 -> 13072 (+1.62%); split: -0.50%, +2.11%
SpillSGPRs: 609 -> 505 (-17.08%)
SpillVGPRs: 946 -> 1145 (+21.04%)
CodeSize: 2537024 -> 2576976 (+1.57%); split: -0.10%, +1.67%
Scratch: 89088 -> 113664 (+27.59%)
MaxWaves: 7150 -> 7134 (-0.22%)
Instrs: 458352 -> 460830 (+0.54%); split: -0.45%, +0.99%
Latency: 6615279 -> 6844092 (+3.46%); split: -0.08%, +3.54%
InvThroughput: 1929504 -> 2044989 (+5.99%); split: -0.22%, +6.21%
VClause: 7186 -> 7338 (+2.12%); split: -0.08%, +2.20%
SClause: 13144 -> 13116 (-0.21%)
Copies: 46152 -> 50127 (+8.61%); split: -0.11%, +8.73%
Branches: 16530 -> 16572 (+0.25%); split: -0.02%, +0.27%
PreSGPRs: 14903 -> 14905 (+0.01%); split: -0.01%, +0.03%
PreVGPRs: 11806 -> 11730 (-0.64%); split: -1.83%, +1.19%

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
 2022-06-27 15:07:27 +00:00
Daniel Schürmann
4235dd7b47 radv: don't lower vectorized instructions to 32bit 
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
 2022-06-27 15:07:27 +00:00
Daniel Schürmann
c298ab0d23 aco: correctly validate v_fma_mixhi_f16 register assignment 
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
 2022-06-27 15:07:27 +00:00
Marcin Ślusarz
b6ba24cd62 anv: disable injection of primitive shading rate for mesh 
It's not needed and causes issues for mesh code (it doesn't
mark the output as per-primitive, which confuses brw_compute_mue_map)

Fixes many tests matching:
dEQP-VK.fragment_shading_rate.dynamic_rendering.*.ms

Fixes: 1542ab70eb ("anv: handle primitive shading rate for mesh")
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16196>
 2022-06-27 14:14:41 +00:00
Marcin Ślusarz
42b551fe7f intel/compiler: adjust task payload offsets as late as possible 
Otherwise passes which expect offsets to be in bytes (like
brw_nir_lower_mem_access_bit_sizes, called from brw_postprocess_nir)
may produce incorrect results.

Fixes 64-bit load/stores in task/mesh shaders.

Fixes: c36ae42e4c ("intel/compiler: Use nir_var_mem_task_payload")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16196>
 2022-06-27 14:14:41 +00:00
Marcin Ślusarz
3dc6a98d78 intel/common: allocate space for at least one task urb 
Fixes: c93cbc77f7 ("intel/common: Add helper for URB allocation in Mesh pipeline")
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16196>
 2022-06-27 14:14:41 +00:00
Emil Velikov
899aa7925b c11: reinstate the original license and authorship 
The original code that was copied in was Boost licensed, so keep that
in. Since Yonggang Luo has code quite some work, keep their copyright
alongside the original one.

Fixes: b2ddec4e98 ("c11: Implement c11/time.h with c11/impl/time.c")
Fixes: e6392fcf3d ("c11: Move the implementation of threads.h into c source code")
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17232>
 2022-06-27 11:46:22 +00:00
Sviatoslav Peleshko
3f6edbc725 intel/blorp: Dirty depth bounds dynamic state bits after blorp 
Blorp emits its own 3DSTATE_DEPTH_BOUNDS, so we'll have to re-emit the
expected state after that.

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Fixes: 56ef501e3a ("blorp: disable depth bounds")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17205>
 2022-06-27 11:11:30 +00:00
Sviatoslav Peleshko
b6bb7f8998 anv: Dirty all dynamic state bits when creating command buffer state 
This makes sure that we'll handle situations when the new state has
the same value as the default one, so we won't dirty some bits, and
consequently will not emit necessary commands (e.g. 3DSTATE_DEPTH_BOUNDS).

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Fixes: 48229d11 ("anv: don't emit 3DSTATE_DEPTH_BOUNDS in pipeline batch")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6722
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17205>
 2022-06-27 11:11:30 +00:00
Marcin Ślusarz
f4386b81e6 intel: fix typos found by codespell 
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17191>
 2022-06-27 10:20:55 +00:00
Boris Brezillon
ab0e09803a dzn: Enable the depthClamp feature 
depthClampEnable is actually the case we support properly.

!depthClampEnable requires extra work to make sure the
depth clamping that's forced by D3D12 is inactive (setting the
viewport depth range to [0,1] and dealing with the actual range
at the shader level), and clamp the depth value read by the
fragment shader in that case. This will be addressed separately.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17231>
 2022-06-27 10:05:56 +00:00
Boris Brezillon
a7d6f52821 dzn: Enable shader{Clip,Cull}Distance 
DXIL has clip/cull distance builtins too.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17231>
 2022-06-27 10:05:55 +00:00
Boris Brezillon
716aeafb67 dzn: Enable dynamic indexing on all kind of descriptors 
nir_to_dxil() supports it.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17231>
 2022-06-27 10:05:55 +00:00
Boris Brezillon
8f4fe3d21f dzn: Advertise shaderImageGatherExtended support 
nir_to_dxil() takes tg4 offsets into account.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17231>
 2022-06-27 10:05:55 +00:00
Boris Brezillon
7988e966fc dzn: Advertise anisotropic filtering support 
We support it already, let's toggle the switch to expose it.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17231>
 2022-06-27 10:05:55 +00:00
Boris Brezillon
ee536ea633 nir/serialize: Put dest last in packed_instr::tex 
packed_instr::tex::dest must be last to match the packed_instr::any::dest
position.

Fixes: 35655865cb ("nir/serialize: pack instructions better")
Cc: stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17212>
 2022-06-27 09:39:22 +00:00
Lionel Landwerlin
68e5265fa1 anv: silence border color swizzle debug message 
MESA-INTEL: debug: gfx11_CreateSampler: ignored VkStructureType 1000411001

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17245>
 2022-06-27 09:01:00 +00:00
Samuel Pitoiset
fd997bde2f radv: dump UMR waves before UMR rings 
Dumping UMR rings might be slow and dumping waves before would make it
more chance to dump them without reporting "No active waves".

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17183>
 2022-06-27 08:36:49 +00:00
Samuel Pitoiset
4c908d4587 radv: fix command line for dumping waves with UMR 
GFXOFF must be disabled before dumping waves and re-enabled after.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17183>
 2022-06-27 08:36:49 +00:00
Samuel Pitoiset
915bc6a179 radv: use RADEON_FLAG_VA_UNCACHED for the trace BO 
Figured this while debugging a GPU hang with a simple CTS test. This
is to make sure data written by the CP are coherent on the CPU.

This also explains spurious GPU hang reports generated for Hitman 3
that made no sense without it. Now it's clear that this game hangs
after a DRAW_INDEX_INDIRECT packet.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17183>
 2022-06-27 08:36:49 +00:00
Samuel Pitoiset
db7890637e radv: disable small primitive culling for user sample locations 
The driver can't assume sample positions at (0.5, 0.5) when user
sample locations are used.

This doesn't fix anything in practice because NGGC is only enabled by
default on GFX10.3 and that extension is currently disabled on GFX10+,
but I would like to expose it at some point.

This fixes dEQP-VK.pipeline.*.sample_locations_ext.verify_location.*
(when the extension is enabled locally).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17228>
 2022-06-27 08:10:08 +00:00
Ella Stanforth
f392b6c1ad v3dv: Implement VK_KHR_performance_query 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14061>
 2022-06-27 07:34:16 +00:00
Erico Nunes
f2a24fd4a2 ci: Revert "CI: Lima farm is offline" 
The lab is up and running again.

This reverts commit 686e20afcd.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17240>
 2022-06-27 07:02:30 +00:00
Qiang Yu
04b15f88e7 radeonsi: replace llvm gs input handle with nir lowering 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
 2022-06-27 11:32:50 +08:00
Qiang Yu
36197b8dc0 ac/llvm: get back nir_intrinsic_load_gs_vertex_offset_amd 
Will be used by radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
 2022-06-27 11:32:46 +08:00
Qiang Yu
e9f1f115fa ac/nir: add triangle_strip_adjacency_fix to gs input lower 
From radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
 2022-06-27 11:32:43 +08:00
Qiang Yu
f8ddee90ca radeonsi: replace llvm es output with nir lowering 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
 2022-06-27 11:32:38 +08:00
Qiang Yu
109eb378e5 ac/nir: change es output lower param to esgs_itemsize 
radeonsi may add extra dword to the stride, so let's pass it
directly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
 2022-06-27 11:32:34 +08:00
Qiang Yu
8b5e8b2af7 ac/nir: remove unused param num_reserved_es_outputs from gs input lower 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
 2022-06-27 11:32:30 +08:00
Qiang Yu
c66eba2072 radeonsi: set lds for gs/es to handle nir shared memory load/store 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
 2022-06-27 11:32:26 +08:00
Qiang Yu
7ddd15f6c7 ac/nir: skip gl_ViewportIndex and gl_Layer write in ES 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
 2022-06-27 11:32:21 +08:00