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Author SHA1 Message Date
Bas Nieuwenhuizen
aba8c579a9 turnip: semaphore support. 
There is only one queue for now, so for non-shared semaphores, the
implementation is basically a no-op. For shared semaphores, this
always uses syncobjs. This depends on syncobj support in the msm
kernel driver.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2769>
 2020-06-26 19:34:17 +00:00
Eric Anholt
6283da34a9 ci/baremetal: Bump the kernel to a recent drm-msm-fixes for msm semaphores. 
We need this to test the new VK feature we're about to land.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2769>
 2020-06-26 19:34:17 +00:00
Daniel Schürmann
5c0f82b0d7 aco: fix partial copies on GFX6/7 
While we don't allow partial subdword copies,
we still need to be able to split 64bit registers

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5663>
 2020-06-26 19:21:57 +00:00
Lepton Wu
66482303f6 mapi: x86: Fix dynamic entries in x86 tsd stubs. 
We need to update dynamic entries related code after updating
asm stubs.

Fixes: 45206d7673 ("mapi: Adapted libglvnd x86 tsd changes")
Signed-off-by: Lepton Wu <lepton@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5598>
 2020-06-26 18:28:01 +00:00
Eric Anholt
63805ccd3f ci/bare-metal: Fail early when we get stuck powering on a cheza. 
I think I've seen about 3 of this error total so far, but waiting 60
minutes for the scripts to give up wastes marge time.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5651>
 2020-06-26 16:54:07 +00:00
Rob Clark
189a0fecf5 freedreno/ir3: move nir finalization to after cache miss 
In cases where every variant is a shader-cache-hit, we never need the
post-finalize round of nir opt/lowering passes.  So defer this until
the first shader-cache-miss to avoid doing pointless work.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
 2020-06-26 08:55:21 -07:00
Rob Clark
f97acb4bb4 freedreno/ir3: disk-cache support 
Adds a shader disk-cache for ir3 shader variants.  Note that builds with
`-Dshader-cache=false` have no-op stubs with `disk_cache_create()` that
returns NULL.

Binning pass variants are serialized together with their draw-pass
counterparts, due to shared const-state.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
 2020-06-26 08:55:19 -07:00
Rob Clark
6aadb00e60 freedreno/ir3: build binning variant at same time as draw variant 
For shader-cache, we are going to want to serialize them together.
Which is awkward if the two related variants are not compiled together.

This also decouples allocation and compile, which will simplify adding
shader-cache (which still needs to allocate, but can skip compile).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
 2020-06-26 08:53:02 -07:00
Rob Clark
83b97bf161 freedreno/a6xx+ir3: stop generating pointless binning shaders 
Currently we always do sysmem if there is tess.  And for GS, the binning
pass VS ends up identical to the draw pass VS, so no point in compiling
it twice.  (For GS what we should do someday is generate a binning pass
GS, and possibly if we can do cross-stage linking opts, an optimized
binning pass VS, but the required outputs would somehow have to end up
in the shader variant key.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
 2020-06-26 08:53:00 -07:00
Rob Clark
fdbe1ffaf7 freedreno/ir3: shuffle some variant fields 
Just to group together the parts that will get serialized when we have
shader disk-cache.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
 2020-06-26 08:43:23 -07:00
Rob Clark
c0f22c3d94 freedreno/ir3: add ir3_compiler_destroy() 
Use ir3_compiler_destroy() rather than open-coding ralloc_free().  This
will give us a place to add more compiler related cleanup code in the
following patches.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
 2020-06-26 08:43:23 -07:00
Rob Clark
f1ab57359c freedreno/ir3: move finalize_nir to pscreen hook 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
 2020-06-26 08:43:22 -07:00
Rob Clark
d3ae559378 freedreno/ir3: add ir3_finalize_nir() 
The next step is to hook this into pscreen->finalize_nir() so it can
come before the state tracker's shader-caching.

Unfortunately we still need to do lower_io after mesa/st, so that is
split out into a post-finalize pass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>
 2020-06-26 08:43:22 -07:00
Mike Blumenkrantz
e35b8971a7 zink: use OpFUnordNotEqual for nir_op_fne 
we want to detect NaNs here, and OpFUnordNotEqual is the variant which does this

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
 2020-06-26 14:07:35 +00:00
Mike Blumenkrantz
765de33d3c zink: set lower_mul_high and lower_rotate in ntv compiler options 
we don't implement these

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
 2020-06-26 14:07:35 +00:00
Mike Blumenkrantz
49c13fccf7 zink: handle isign alu in ntv 
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
 2020-06-26 14:07:35 +00:00
Mike Blumenkrantz
21fe5b0ffd zink: handle ixor in ntv 
fixes spec@glsl-1.30@execution@built-in-functions@fs-op-assign-bitxor tests

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
 2020-06-26 14:07:35 +00:00
Mike Blumenkrantz
651d093298 zink: lower byte/word extract ops in nir 
we don't implement these, and pre-optimizing them breaks things in ntv->vtn

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
 2020-06-26 14:07:35 +00:00
Mike Blumenkrantz
90d3455848 zink: add bitfield_reverse handling to ntv 
fixes several piglit tests

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
 2020-06-26 14:07:35 +00:00
Mike Blumenkrantz
957d8e2658 zink: add ult handling for ntv 
fixes shaders@glsl-vs-absolutedifference-uint piglit test

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
 2020-06-26 14:07:35 +00:00
Mike Blumenkrantz
2159aa0c49 zink: handle signed and unsigned min/max ops in ntv 
fixes a number of piglit amd_shader_trinary_minmax tests

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>
 2020-06-26 14:07:35 +00:00
Samuel Pitoiset
f13d79f519 radv: remove the load/store workaround for Monster Hunter World with LLVM 
Now that ACO is default, this is pointless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5658>
 2020-06-26 14:42:44 +02:00
Samuel Pitoiset
a30ad8cb23 radv: remove the shader ballot workaround for Youngblood with LLVM 
Now that ACO is default, this is now pointless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5658>
 2020-06-26 14:42:42 +02:00
Erik Faye-Lund
099916384a docs: update favicon 
I created a new and cleaner favicon for mesa3d.org, and it seems like a
good idea to use that one for the docs as well.

While we're at it, replace the original PNG with the original SVG asset
the ICO-file was generated from.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5643>
 2020-06-26 12:09:22 +00:00
Jonathan Marek
2fbc12a0ac turnip: fix huge scissor min/max case 
Now that tu_cs_emit_regs is used for the scissor, it hits an assert when
the scissor is too large. Fixes this dEQP test:

dEQP-VK.draw.scissor.static_scissor_max_int32

Fixes: 9c0ae5704d ("turnip: fix empty scissor case")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5655>
 2020-06-26 11:34:49 +00:00
Jonathan Marek
1854eeefde turnip: fix VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES 
My attempt to be clever here backfired, it overwrites the pNext and stops
the loop (causing deqp to fail to query extension features after that).

Fixes: 62de79ac44 ("turnip: implement VK_KHR_shader_draw_parameters")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5654>
 2020-06-26 11:11:29 +00:00
Icecream95
6b886fbc0b panfrost: Add PAN_MESA_DEBUG=gl3 flag 
This flag allows forcing GL 3.3 without having to use
MESA_GL_VERSION_OVERRIDE etc.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5584>
 2020-06-26 10:30:03 +00:00
Connor Abbott
1288613f1c freedreno/a6xx: use firstIndex field 
Analogous to the turnip change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
 2020-06-26 10:05:24 +00:00
Connor Abbott
ba5e1c5310 tu: Pass firstIndex directly to CP_DRAW_INDX_OFFSET 
Saves some minor overhead, cleans things up a bit, and removes one more
unknown. We now program the internal registers in the same way between
direct/indirect draws.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
 2020-06-26 10:05:24 +00:00
Connor Abbott
259d07a2ff freedreno/registers: Label firstIndex field in CP_DRAW_INDX_OFFSET 
Based on comparing the implementations of CP_DRAW_INDX_OFFSET and
CP_DRAW_INDIRECT, this is what this field is for.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
 2020-06-26 10:05:24 +00:00
Connor Abbott
a32fb2f9d0 freedreno: On a5xx+ INDX_SIZE is MAX_INDICES 
This was already done correctly for the indirect variants, and turnip
was setting the correct value, but it seems freedreno missed the change
in the non-indirect variant. Also, fix a misspelling of "indices" and
add a type to INDX_SIZE.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
 2020-06-26 10:05:24 +00:00
Connor Abbott
1dd24bf27b freedreno: Share constlen between different stages properly 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
 2020-06-26 09:34:33 +00:00
Connor Abbott
d9dd989d2a freedreno: Refactor ir3_cache shader compilation 
Use an array, which makes it more like turnip and makes implementing the
const limits easier.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
 2020-06-26 09:34:33 +00:00
Connor Abbott
8ad65609da tu: Share constlen between different stages properly 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
 2020-06-26 09:34:33 +00:00
Connor Abbott
48b1602b50 ir3: Add ir3_trim_constlen() 
This provides the policy for how to handle reducing constlen for some
stages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
 2020-06-26 09:34:33 +00:00
Connor Abbott
9edff0cfd4 ir3: Support variants with different constlen's 
This provides the mechanism for compiling variants with a reduced
constlen. The next patch provides the policy for choosing which to
reduce.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
 2020-06-26 09:34:33 +00:00
Connor Abbott
4554b946c3 ir3: Include ir3_compiler from ir3_shader 
I wanted to access the ir3_compiler from a small helper inside
ir3_shader.h, which currently isn't possible.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
 2020-06-26 09:34:33 +00:00
Connor Abbott
2841bb1fac ir3, freedreno: Round up constlen earlier 
Prevents problems when calculating whether we overflow the shared limit.
Note that on a6xx, the macros handle the assert for us.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
 2020-06-26 09:34:33 +00:00
Iago Toral Quiroga
4845f184d7 v3d/compiler: don't rewrite unused temporaries to point to NOP register 
This was assuming that unused temporaries are written but never read,
since the NOP register can only be used as a destination register,
but we can end up here also for temporaries that are read once but
never written.

This was found with a graphicsfuzz test that has a switch with
cases that have unreachable discards. In that test, NIR genrates
code like this:

decl_reg vec3 32 r19
...
r20 = mov r19.z
r21 = mov r19.y
r22 = mov r19.x

Where r19.xyz would generate 3 temporary registers that are read but
never written, so we would rewrite them to point to the NOP register
as QPU instruction sources, which is not allowed and would hit an
assert that expect magic reads to be from [r0,r5] only.

Fixes:
dEQP-VK.graphicsfuzz.unreachable-switch-case-with-discards

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5645>
 2020-06-26 08:57:32 +00:00
Neil Roberts
3b1c511b09 v3d: Use stvpmd for non-uniform offsets in GS 
The offset for the VPM write for storing outputs from the geometry
shader isn’t necessarily uniform across all the lanes. This can happen
if some of the lanes don’t emit some of the vertices. In that case the
offset for the subsequent vertices will be different in each lane. In
that case we need to use the stvpmd instruction instead of stvpmv
because it will scatter the values out.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3150

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5621>
 2020-06-26 09:36:15 +02:00
Neil Roberts
dab8a9169c v3d: Add missing macro for stvpmd instruction 
stvpmd is like stvpmv but it scatters the output. It can be used with
non-dynamically uniform offsets.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5621>
 2020-06-26 09:36:15 +02:00
Marek Olšák
71794567f9 radeonsi: remove tabs 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák
0cdec11d95 radeonsi: clear per-context buffers at the end of si_create_context 
We don't want any packets before CONTEXT_CONTROL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák
da78d50bc8 radeonsi: make si_pm4_cmd_begin/end static and simplify all usages 
There is no longer the confusing trailing si_pm4_cmd_end call.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák
7b2a0f880b radeonsi: disallow adding BOs into si_pm4_state except 1 shader BO per state 
The si_shader pointer is already there, so use it and remove the array
of BOs.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák
3b1e42d2c2 radeonsi: make wait_mem_scratch unmappable 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák
428360662f radeonsi: don't add the tess ring buffers into the cs_preamble state 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák
1c1d34a67a radeonsi: rename init_config states to cs_preamble states 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák
bbc0a2d51d radeonsi: don't add the border color buffer into the init_config state 
We might have to replace init_config for preemption.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák
c7680625c3 ac,winsys/amdgpu: align IBs the same as the kernel 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00