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Author SHA1 Message Date
Jonathan Marek
aab3398b33 turnip: improve dirty bit handling a bit 
This moves some logic out of bind_draw_states, moving towards the eventual
goal of doing very little in bind_draw_states.

Split this out as a separate patch to make the DIRTY_INPUT_ATTACHMENTS more
visible: it can be safely removed because pipelines are subpass specific,
so there will always be a pipeline change to go with the CmdBeginRenderPass
and CmdNextSubpass (the CmdBindPipeline may not be in the subpass, but the
draw that flushes the pipeline update will be).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5446>
 2020-06-17 15:32:30 +00:00
Jonathan Marek
edb8c581db turnip: move descriptor set BO tracking to CmdBindDescriptorSets 
This avoids the duplicated code.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5446>
 2020-06-17 15:32:30 +00:00
Jonathan Marek
5ef0f9f622 turnip: compute and graphics have completely separate state 
The comment about fragment shader state overwriting compute shader state
is wrong, if either path is overwriting the other's state then it is a
mistake.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5446>
 2020-06-17 15:32:30 +00:00
Connor Abbott
a3464c567c tu: Actually remove dead variables after io lowering 
I forgot that their derefs would still be lying around, so we need to
eliminate them first.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5519>
 2020-06-17 14:36:50 +00:00
Connor Abbott
168c42290f ir3: Don't calculate num_samp ourselves 
In addition to duplicating what core NIR does better, this was wrong for
Vulkan, where it should be 0 as there are no non-bindless samplers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5519>
 2020-06-17 14:36:50 +00:00
Connor Abbott
568e06b3a6 tu: Set num_components to 0 when building bindless intrinsics 
Fixes: 167fa288 (" nir/validate: validate intr->num_components")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5520>
 2020-06-17 15:49:40 +02:00
Connor Abbott
6fcbce3b99 tu: Remove tu_shader_compile_options 
The only two fields were always true, and I don't think we'd ever have
use for them. If we want to disable optimizations then we'd need a
different approach, and I don't even know what include_binning_pass was
for.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5500>
 2020-06-17 13:13:05 +00:00
Connor Abbott
808992fc50 tu: Use the ir3 shader API 
This will be necessary once we start compiling multiple variants due to
different const size limits, and it will also be necessary for properly
implementing the pipeline cache.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5500>
 2020-06-17 13:13:05 +00:00
Connor Abbott
b1700698a5 tu: Remove num_samp hack 
Delete the variables so that ir3 thinks there are no samplers and
images instead.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5500>
 2020-06-17 13:13:05 +00:00
Connor Abbott
6f2981176d ir3: Pass reserved_user_consts to ir3_shader_from_nir() 
ir3_shader_from_nir() calls ir3_optimize_nir(), which currently sets up
the const state. However, we need to know the number of user consts
reserved by the driver before setting up the const state, which means
that this information needs to be passed into ir3_shader_from_nir()
somehow rather than being set in the shader.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5500>
 2020-06-17 13:13:05 +00:00
Alyssa Rosenzweig
89c8393a16 pan/mdg: Reassociate adds for multiply-by-two 
Only a single shader-db change it looks like, and not even from
scheduling, no fun.

instructions helped:   shader31 MESA_SHADER_FRAGMENT:                    64 -> 63 (-1.56%)
quadwords helped:   shader31 MESA_SHADER_FRAGMENT:                    66 -> 65 (-1.52%)
registers HURT:   shader31 MESA_SHADER_FRAGMENT:                    2 -> 3 (50.00%)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5475>
 2020-06-17 12:57:34 +00:00
Alyssa Rosenzweig
a3348f88c8 pan/mdg: Canonicalize (x * 2.0) to (x + x) 
This lets the previous commit kick in to schedule to either a multiply
or an add. GLES2 shader-db:

total instructions in shared programs: 50514 -> 50459 (-0.11%)
instructions in affected programs: 7436 -> 7381 (-0.74%)
helped: 14
HURT: 7
helped stats (abs) min: 2 max: 8 x̄: 5.00 x̃: 5
helped stats (rel) min: 0.95% max: 1.14% x̄: 1.07% x̃: 1.08%
HURT stats (abs)   min: 2 max: 3 x̄: 2.14 x̃: 2
HURT stats (rel)   min: 0.85% max: 8.57% x̄: 2.73% x̃: 1.26%
95% mean confidence interval for instructions value: -4.37 -0.87
95% mean confidence interval for instructions %-change: -0.91% 1.31%
Inconclusive result (%-change mean confidence interval includes 0).

total bundles in shared programs: 25680 -> 25573 (-0.42%)
bundles in affected programs: 6148 -> 6041 (-1.74%)
helped: 37
HURT: 7
helped stats (abs) min: 1 max: 9 x̄: 3.14 x̃: 2
helped stats (rel) min: 0.63% max: 8.33% x̄: 2.02% x̃: 2.13%
HURT stats (abs)   min: 1 max: 2 x̄: 1.29 x̃: 1
HURT stats (rel)   min: 0.88% max: 11.11% x̄: 3.92% x̃: 1.30%
95% mean confidence interval for bundles value: -3.32 -1.54
95% mean confidence interval for bundles %-change: -2.00% -0.14%
Bundles are helped.

total quadwords in shared programs: 40887 -> 40815 (-0.18%)
quadwords in affected programs: 14203 -> 14131 (-0.51%)
helped: 61
HURT: 2
helped stats (abs) min: 1 max: 4 x̄: 1.21 x̃: 1
helped stats (rel) min: 0.16% max: 11.11% x̄: 1.11% x̃: 0.57%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 2.86% max: 4.00% x̄: 3.43% x̃: 3.43%
95% mean confidence interval for quadwords value: -1.32 -0.96
95% mean confidence interval for quadwords %-change: -1.46% -0.48%
Quadwords are helped.

total registers in shared programs: 3916 -> 3913 (-0.08%)
registers in affected programs: 46 -> 43 (-6.52%)
helped: 5
HURT: 1
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 10.00% max: 33.33% x̄: 14.89% x̃: 10.00%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for registers value: -1.79 0.79
95% mean confidence interval for registers %-change: -33.51% 25.37%
Inconclusive result (value mean confidence interval includes 0).

total threads in shared programs: 2455 -> 2454 (-0.04%)
threads in affected programs: 5 -> 4 (-20.00%)
helped: 1
HURT: 1
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%

total loops in shared programs: 6 -> 6 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 168 -> 168 (0.00%)
spills in affected programs: 0 -> 0
helped: 0
HURT: 0

total fills in shared programs: 186 -> 186 (0.00%)
fills in affected programs: 0 -> 0
helped: 0
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5475>
 2020-06-17 12:57:34 +00:00
Alyssa Rosenzweig
6318e46141 pan/mdg: Allow scheduling "x + x" to multipliers 
One of the neat things with Midgard's wacky VLIW... on VADD/SADD this is
(x + x) literally, on VMUL/SMUL/VLUT this is (x * 2.0) where the 2.0 is
exactly representable in FP16 so it fits nicely as an inline constant.
So we don't need to restrict its scheduling.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5475>
 2020-06-17 12:57:34 +00:00
Alyssa Rosenzweig
bc356abea3 pan/mdg: Factor out unit check 
We'd like to do something a bit more complicated.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5475>
 2020-06-17 12:57:34 +00:00
Rhys Perry
de7c6950b3 aco: fix sub-dword opsel/sdwa checks 
These should all check if the operand has a regclass. The opsel check
should also be skipped post-RA.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5504>
 2020-06-17 10:57:17 +00:00
Rhys Perry
1e791e51a6 aco: fix validation error from vgpr spill/restore code 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5504>
 2020-06-17 10:57:17 +00:00
Jonathan Marek
d37deebde5 turnip: fix cubic filtering with CmdBlitImage 
This fixes the newly added cubic blit_image tests for A650, by falling back
to the 3D path and setting the filter correctly.

Note: there are still failures with the texture filtering tests.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5509>
 2020-06-17 08:50:42 +00:00
Jonathan Marek
198b13974a turnip: fix 3D path always being used for CmdBlitImage 
This change accidentally made it into 72d7df40a5, and started causing
blit_image flakes (because of the issue fixed in the previous patch)

Fixes: 72d7df40a5 ("turnip: add layered 3D path clear for CmdClearAttachments")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5509>
 2020-06-17 08:50:42 +00:00
Jonathan Marek
1622787ee4 turnip: set VFD_INDEX_OFFSET in 3D clear/blit path 
This was missing an causing flakes when used after a test that set it to
a non-zero value.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5509>
 2020-06-17 08:50:42 +00:00
Samuel Pitoiset
4d13e35315 spirv: do not set num_components for non-vectorized mbcnt_amd intrinsic 
Fixes: 167fa2887f ("nir/validate: validate intr->num_components")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5493>
 2020-06-17 06:57:13 +00:00
Timothy Arceri
b2e9d21fdd st_glsl_to_nir: fix potential use after free 
When updating the shader info used by GL for the API we must
remember to make sure to restore the pointers to its own name
and label strings. There are a number of ways in which the nir
copy of these strings can be freed before GL is finished with
them.

Fixes: 36be8c2fcf ("st/glsl_to_nir: use nir_shader_gather_info()")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2875

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5488>
 2020-06-17 11:35:38 +10:00
Timothy Arceri
7e8e02d543 glsl: small optimisation fix for uniform array resizing 
The fix in the previous patch removed an erronous attempt to skip
resizing variable types in each stage. Now that has been removed
iterating over each shader stage is no longer required here.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5487>
 2020-06-17 01:06:27 +00:00
Timothy Arceri
a5d3e061af glsl: fix uniform array resizing in the nir linker 
The initial support tried to match uniform variables from different
shaders based on the variables pointer. This will obviously never
work, instead here we use the variables name whcih also means we
must disable this optimisation for spirv.

Using the base variable name works because when collecting uniform
references we never iterate past the first array dimension, and
only support resizing 1D arrays (we also don't support resizing
arrays inside structs).

We also drop the resized bool as we can't skip processing the var
just because is was resized in another shader, we must resize
the var in all shaders.

Fixes: a34cc97ca3 ("glsl: when NIR linker enable use it to resize uniform arrays")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3130

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5487>
 2020-06-17 01:06:27 +00:00
Iván Briano
f63a578100 anv: Add VK_EXT_custom_border_color to relnotes 
Missed it on 5425968d2e

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5136>
 2020-06-17 00:48:39 +00:00
Iván Briano
ed7bebc17b anv: enable VK_EXT_pipeline_creation_cache_control 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5136>
 2020-06-17 00:48:39 +00:00
Iván Briano
23633f6c69 anv: implement VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT 
v2:
* Set pPipeline to NULL in the corresponding
  graphics/compute_create_pipeline function.
* Keep current ANV behavior of bailing on the first real error.

v3:
* Don't return early if the pipeline succeeded.

v:4(5?):
* Simplify return conditions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5136>
 2020-06-17 00:48:39 +00:00
Iván Briano
13f44596d7 anv: support externally synchronized pipeline caches 
Implement the VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT
bits of the VK_EXT_pipeline_creation_cache_control extension.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5136>
 2020-06-17 00:48:39 +00:00
Sagar Ghuge
a0ef4971d0 intel/compiler: Remove unnecessary optimization for MUL 
2 source instruction only support immediate for src1 operand, so no
point in adding optimization condition for src0 oprand.

v2:
- Update commit message and don't remove ADD optimization (Matt Turner)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5341>
 2020-06-16 17:11:32 -07:00
Sagar Ghuge
d4f3f9390f intel/compiler: Optimize integer add with 0 into mov 
Kaby Lake
total instructions in shared programs: 326560 -> 323616 (-0.90%)
instructions in affected programs: 178062 -> 175118 (-1.65%)
helped: 129
HURT: 0
helped stats (abs) min: 1 max: 118 x̄: 22.82 x̃: 8
helped stats (rel) min: 0.35% max: 6.56% x̄: 2.57% x̃: 2.47%
95% mean confidence interval for instructions value: -27.71 -17.93
95% mean confidence interval for instructions %-change: -2.81% -2.32%
Instructions are helped.

total cycles in shared programs: 43741127 -> 45397851 (3.79%)
cycles in affected programs: 40880261 -> 42536985 (4.05%)
helped: 94
HURT: 34
helped stats (abs) min: 5 max: 6160 x̄: 598.91 x̃: 45
helped stats (rel) min: 0.20% max: 34.86% x̄: 2.52% x̃: 1.09%
HURT stats (abs)   min: 1 max: 76198 x̄: 50383.00 x̃: 69677
HURT stats (rel)   min: 0.07% max: 48.41% x̄: 15.65% x̃: 6.49%
95% mean confidence interval for cycles value: 8023.10 17863.21
95% mean confidence interval for cycles %-change: <.01% 4.60%
Cycles are HURT.

total spills in shared programs: 1086 -> 978 (-9.94%)
spills in affected programs: 897 -> 789 (-12.04%)
helped: 24
HURT: 0

total fills in shared programs: 1686 -> 1584 (-6.05%)
fills in affected programs: 1371 -> 1269 (-7.44%)
helped: 24
HURT: 0

v2:
- Use brw_reg_type_is_integer (Matt Turner)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5341>
 2020-06-16 16:54:27 -07:00
Jan Beich
63b81c9915 meson: unbreak sysctl.h detection on BSDs 
Code:
 #include <sys/sysctl.h>
Compiler stdout:

Compiler stderr:
 In file included from testfile.c:1:
/usr/include/sys/sysctl.h:1184:40: error: unknown type name 'size_t'
int     sysctl(const int *, u_int, void *, size_t *, const void *, size_t);
                                           ^
/usr/include/sys/sysctl.h:1185:40: error: unknown type name 'size_t'
int     sysctlbyname(const char *, void *, size_t *, const void *, size_t);
                                           ^
/usr/include/sys/sysctl.h:1186:42: error: unknown type name 'size_t'
int     sysctlnametomib(const char *, int *, size_t *);
                                             ^
3 errors generated.

Checking if "sys/sysctl.h" compiles: NO

<https://gitlab.freedesktop.org/mesa/drm/-/commit/1f8ada802391>
<https://gitlab.freedesktop.org/mesa/drm/-/commit/4083e8f2c659>

Reviewed-by: Niclas Zeising <zeising@daemonic.se>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5462>
 2020-06-16 23:24:54 +00:00
Eric Anholt
2a80f96b51 docs: Add dri-devel to the mailing lists and drop the DRI wiki link. 
The DRI wiki is a wasteland at this point, let's just fold the one bit of
useful information in here.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5507>
 2020-06-16 22:09:47 +00:00
Jan Beich
46c368907f util: enable futex usage on BSDs after 7dc2f47882 
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5460>
 2020-06-16 21:44:35 +00:00
Rob Clark
680ca5b393 freedreno/ir3: add post-scheduler cp pass 
A pass to eliminate extra mov's from an array.  We need to do this after
scheduling so we know that there are not any potentially conflicting
array writes between the original `mov` and it's use(s).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2124
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
 2020-06-16 20:56:15 +00:00
Rob Clark
a60d48a863 freedreno/ir3/cp: extract valid_flags 
We'll also need this in the postsched-cp pass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
 2020-06-16 20:56:15 +00:00
Rob Clark
5f1f8f7b17 freedreno/ir3: delay test support for vectorish instructions 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
 2020-06-16 20:56:15 +00:00
Rob Clark
92d6eb4dd5 freedreno/ir3: add helpers to move instructions 
A bit cleaner than open coding the list manipulation.  Plus I want to
use it in the next patch, rather than adding more open coded list
futzing.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
 2020-06-16 20:56:15 +00:00
Rob Clark
9eed0c6011 freedreno/ir3/delay: calculate delay properly for (rptN)'d instructions 
When a sequence of same instruction is encoded with repeat flag,
destination registers are written on successive cycles.  Teach the
delay calculation about this.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
 2020-06-16 20:56:15 +00:00
Rob Clark
c3b30963dd freedreno/ir3: add test for delay slot calculation 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
 2020-06-16 20:56:15 +00:00
Rob Clark
a69d28769a freedreno/ir3/print: print (r) flag 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
 2020-06-16 20:56:15 +00:00
Rob Clark
cd376a1434 freedreno/ir3/legalize: don't allow (nopN) if (rptN) 
These two encodings are mutually exclusive.  If the instruction is a
vector(ish) `(rptN)` instruction, then we can't fold a `(nopN)` post-
delay into it.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
 2020-06-16 20:56:15 +00:00
Rob Clark
1418ea0d00 freedreno/a6xx: emit shader names in debug builds 
To simplify mapping a shader in a cmdstream trace back to glsl.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
 2020-06-16 20:56:15 +00:00
Rob Clark
541c288b5f freedreno: splitup emit_string_marker 
So that we can use it internally to emit string markers into a specified
rb.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
 2020-06-16 20:56:15 +00:00
Rob Clark
f35f711c71 freedreno/ir3/cp: properly handle already-folded RELATIV 
In the `try_swap_mad_two_srcs()` case, valid_flags() gets called both
for the src that we want to try to fold, and for the other src that we
are trying to swap to make that possible.  It can happen in the 2nd case
that a RELATIV src has already been folded.  Since `ssa()` returns non-
null in both the `IR3_REG_SSA` and `IR3_REG_ARRAY` cases (in the later
case, it is the dependent array access that the current instruction
cannot be moved ahead of), we need to explicitly check that the src
reg we are looking at is still an SSA src.

Reported-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
 2020-06-16 20:56:15 +00:00
Rob Clark
1bee79996b freedreno/ir3/validate: also check instr->address 
Verify that instructions which have a relative src and/or dest, have
`instr->address`.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
 2020-06-16 20:56:15 +00:00
Rob Clark
f598786775 freedreno/sched: reset delay counters at start of block 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
 2020-06-16 20:56:15 +00:00
Rob Clark
6717fd5719 freedreno/log-parser: fix compute times 
We also need to clear the table of compute times at the end of the
frame, otherwise results shown will include all the compute jobs since
the beginning of the trace.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
 2020-06-16 20:56:15 +00:00
Eric Anholt
8ea5d8ce83 docs: Replace ancient swrast conformance docs with more current information. 
I don't think Mesa 4.0 swrast conformance is relevant at this point, just
point people to the current Khronos list.  Also, add some more information
on submitting results.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5482>
 2020-06-16 20:54:44 +00:00
Erik Faye-Lund
429ff05491 docs/relnotes: update internal references 
This time, let's use proper Sphinx roles for the referenes, so we can
reference documents and inline refs.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5471>
 2020-06-16 20:36:38 +00:00
Erik Faye-Lund
9be0e2dbf4 docs: update internal references 
This time, let's use proper Sphinx roles for the referenes, so we can
reference documents and inline refs.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5471>
 2020-06-16 20:36:38 +00:00
Lionel Landwerlin
762706c5a6 anv: add an option to disable secondary command buffer calls 
Those are currently hurting Felix' ability to look at the batches.

We can probably detect this in the aubinator but that's a bit more
work than falling back to the previous behavior.

v2: Condition VK_KHR_performance_query to not using this variable (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5391>
 2020-06-16 20:23:52 +00:00