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239 Commits

Author SHA1 Message Date
Marek Olšák
980b7f75e8 amd: enable gfx11 in header generator, fix drivers with renamed gfx6-10 defs 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
 2022-05-10 04:29:54 +00:00
Dave Airlie
1ec4e568de radv: abstract queue family away from queue family index. 
If we introduce another queue type (video decode) we can have a
disconnect between the RADV_QUEUE_ enum and the API queue_family_index.

currently the driver has
GENERAL, COMPUTE, TRANSFER which would end up at QFI 0, 1, <nothing>
since we don't create transfer.

Now if I add VDEC we get
GENERAL, COMPUTE, TRANSFER, VDEC at QFI 0, 1, <nothing>, 2
or if you do nocompute
GENERAL, COMPUTE, TRANSFER, VDEC at QFI 0, <nothing>, <nothing>, 1

This means we have to add a remapping table between the API qfi
and the internal qf.

This patches tries to do that, in theory right now it just adds
overhead, but I'd like to exercise these paths.

v2: add radv_queue_ring abstraction, and pass physical device in,
as it makes adding uvd later easier.
v3: rename, and drop one direction as unneeded now, drop queue_family_index
from cmd_buffers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13687>
 2022-03-11 04:38:55 +00:00
Samuel Pitoiset
a224b7a057 radv: fix allocating/uploading the trap handler shader 
Since shaders are allocated per pipeline, the trap handler shader
was not uploaded at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14950>
 2022-02-14 08:31:10 +01:00
Samuel Pitoiset
c47b8d7bf3 radv: optimize CPU overhead of si_cp_dma_prefetch() slightly 
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5008
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14618>
 2022-01-21 20:15:52 +00:00
Marek Olšák
3ea5beca1f radv: apply spi_cu_en to CU_EN 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14122>
 2022-01-05 01:36:10 -05:00
Marek Olšák
955c6de1c1 radv: set COMPUTE_DESTINATION_EN_SEn to spi_cu_en 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14122>
 2022-01-05 01:36:10 -05:00
Bas Nieuwenhuizen
6968c87e97 radv: Add named constants for max framebuffer width/height. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13721>
 2021-12-05 17:21:32 +00:00
Samuel Pitoiset
e04101c34e radv: only emit PGM_LO for the vertex prolog 
Shaders are allocated in the 32-bit address space.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13551>
 2021-11-09 10:13:38 +00:00
Samuel Pitoiset
9b80f4d5f2 radv: rename radv_shader_variant to radv_shader 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13548>
 2021-11-01 20:04:45 +00:00
Bas Nieuwenhuizen
fd8210f27e radv: Try to do a better job of dealing with L2 coherent images. 
Only try to invalidate L2 if we actually hit one of the incoherent images.

Note we may actually insert some extra flushes at the end of a command
buffer so that we may asume the caches are clean the start of the next
command buffer. However, on average I think that case is uncommon
enough that being able to make assumptions at the start of a cmdbuffer
is beneficial. Especially since MSAA is somewhat rare in more recent
games.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13239>
 2021-10-13 14:07:05 +00:00
Rhys Perry
404752bfb2 radv: add radv_shader_variant_get_va and radv_find_shader_variant helpers 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
 2021-10-13 05:13:10 +00:00
Samuel Pitoiset
55e6a68f69 radv: disable the DX10 diamond test for better line rasterization perf 
Ported from RadeonSI. PAL also doesn't enable it for Vulkan.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13066>
 2021-10-04 07:21:51 +00:00
Timur Kristóf
cb05c85abd radv: Disable HW generated edge flags for NGG shaders. 
Vulkan doesn't support user edge flags, and also doesn't have
any decomposed primitives where drawing internal edges should
be disallowed. Hence, we don't need this.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12998>
 2021-09-23 15:52:26 +02:00
Samuel Pitoiset
971a373caf radv: use radeon_set_sh_reg_seq() more for initial gfx/compute state 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12671>
 2021-09-01 20:46:29 +00:00
Samuel Pitoiset
e0353296da radv: allocate shaders to 32-bit address to skip PGM_HI 
This reduces the number of emitted registers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12466>
 2021-08-23 11:28:21 +00:00
Timur Kristóf
d911259c3a radv: Use ac_compute_late_alloc in radv_pipeline. 
This aligns RADV with RadeonSI in how it handles late alloc,
making it easier for us to deal with deadlocks and such.

Also move setting the RSRC3 registers for VS, GS and NGG
into radv_pipeline.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11905>
 2021-08-04 15:37:05 +00:00
Samuel Pitoiset
87b0962fef radv: do not use radeon_set_context_reg_seq() for only one register 
radeon_set_context_reg() is a shortcut for that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12099>
 2021-07-30 17:05:38 +02:00
Pierre-Eric Pelloux-Prayer
3914bd457b amd/registers: fix fields conflict detection 
The existing code handled the case where the new definition of the
same field was larger than the old one.
This commit adds a check to handle the reverse case: the new def
is smaller than the old one (= so writing using the merged macro
would affect the next fields).

The affected fields are:
* LGKM_CNT (in SQ_WAVE_IB_STS)
* DONUT_SPLIT (in VGT_TESS_DISTRIBUTION)
* HEAD_QUEUE (in GDS_GWS_RESOURCE)

DONUT_SPLIT is the only one used by radeonsi/radv.

Fixes: e6184b0892 ("amd/registers: scripts for processing register descriptions in JSON")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12063>
 2021-07-30 08:50:38 +00:00
Mike Blumenkrantz
1e13cb1965 radv: merge si_write_viewport into radv_emit_viewport 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11839>
 2021-07-16 15:22:46 +00:00
Timur Kristóf
ed163a44b6 radv: Expose radv_get_viewport_xform in radv_private.h 
We need to emit viewport transform information for culling shaders.
This is used for small primitive culling.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10525>
 2021-07-13 23:56:33 +00:00
Marek Olšák
66f254b4e6 radeonsi,radv: fix a late alloc deadlock with <= 6 CUs per SA 
We should always prevent 1 CU from executing VS and GS waves
to prevent a deadlock.

Fixes: c377f45c18 "radeonsi/gfx10: rewrite late alloc computation"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>
 2021-07-08 18:37:41 +00:00
Timur Kristóf
4fcb7e96b8 radv: Set parameter cache oversubscription according to the PC lines. 
This matches how RadeonSI also sets this register.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11711>
 2021-07-08 16:54:29 +02:00
Bas Nieuwenhuizen
f9cc94af7b radv/winsys: Add support for a fixed VA address for replay. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10570>
 2021-07-05 17:27:51 +00:00
Bas Nieuwenhuizen
8025b4120f radv/winsys: Return vulkan errors for buffer creation. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10570>
 2021-07-05 17:27:51 +00:00
Samuel Pitoiset
380742b9f3 radv: fix missing default state for DB_DFSM_CONTROL 
Fixes: 69ae02151d ("radv: remove DFSM")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11028>
 2021-05-27 11:48:29 +00:00
Samuel Pitoiset
c40d7fadc3 radv: implement dynamic primitive restart enable 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10340>
 2021-05-06 20:58:59 +00:00
Bas Nieuwenhuizen
057ec395a4 radv: Refactor cs_domain to be a winsys function. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10198>
 2021-04-14 15:16:17 +00:00
Bas Nieuwenhuizen
59c501ca35 radv: Format. 
Using

find ./src/amd/vulkan -regex '.*/.*\.\(c\|h\|cpp\)' | xargs -P8 -n1 clang-format --style=file -i

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10091>
 2021-04-10 03:31:58 +02:00
Samuel Pitoiset
549f41754a radv: use explicit VRS mode when configuring PA_CL_VRS_CNTL 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7794>
 2021-04-09 14:47:52 +02:00
Marek Olšák
b3e7c77f13 amd: fix parsing the last dword of DMA_DATA packets 
It was parsing it as SQ_WAVE_GPR_ALLOC instead of COMMAND.
Change the offset to an odd number to work around it.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
 2021-04-02 12:05:00 +00:00
Samuel Pitoiset
f5540209ab radv: enable VRS 2x2 coarse shading for flat shading on GFX10.3+ 
This should safe to enable and shouldn't degrade the quality.
It decreases the number of PS invocations by 4 when used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9515>
 2021-03-22 12:36:26 +01:00
Samuel Pitoiset
88f42ea93e radv: emit the trap handler registers earlier 
Directly into the GFX init IB.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9076>
 2021-02-19 08:58:19 +00:00
Rhys Perry
d906c007d6 radv: use a more relaxed alignment for upload buffer allocations 
256 bytes was higher than necessary.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8833>
 2021-02-11 11:44:06 +00:00
Samuel Pitoiset
e02b1577d0 radv/winsys: remove the radv_amdgpu_winsys_bo::ws indirection 
This saves a 64-bit pointer from radv_amdgpu_winsys_bo and it's
also common to pass a winsys pointer as the first parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
 2021-02-08 08:45:38 +01:00
Samuel Pitoiset
64ed873405 radv: remove radv_util.h 
util_bitcount() is already defined in src/util/bitscan.h.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8711>
 2021-01-26 17:31:03 +01:00
Samuel Pitoiset
23461897fe radv: add support for emitting PS_DONE/CS_DONE on GFX6-8 
On GFX6, EOS events are always emitted with EVENT_WRITE_EOS.
On GFX7+, EOS events are emitted with EVENT_WRITE_EOS on the
graphics queue, and with RELEASE_MEM on the compute queue.

Fixes: 9c65f1f111 ("radv: synchronize Cmd{Set,Write}Event() using PS_DONE/CS_DONE events")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8710>
 2021-01-26 09:26:58 +00:00
Samuel Pitoiset
c3ac6f7cd7 radv: flush L2 metadata as part of CB/DB flush instead of CS_DONE on GFX9 
This restores the previous logic because L2 coherency was fully
implemented. It appears that flushing L2 metadata with a CS_DONE
event hangs.

This fixes GPU hangs with Monster Hunter World.

Fixes: 4a783a3c ("radv: Use L2 coherency on GFX9+.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8566>
 2021-01-19 07:47:34 +01:00
Samuel Pitoiset
c6849f9687 radv: do not invalidate the L2 metadata cache on compute queues 
The flush VA space was only allocated for command buffers on the
graphics queue. Also, the ZPASS_DONE event should never be emitted
on compute queues because it hangs.

Invalidating the L2 metadata cache is only required for coherency
between the RBs and L2, so only on the graphics queue.

The L2 cache is invalidated at beginning of any IBs and that should
also invalidate the L2 metadata cache for compute anyways.

Fixes: 4a783a3c ("radv: Use L2 coherency on GFX9+.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8494>
 2021-01-15 07:36:11 +01:00
Bas Nieuwenhuizen
4a783a3c78 radv: Use L2 coherency on GFX9+. 
Especially on GFX10 we can avoid pretty much all L2 flushes.

However, instead of that we have to do L2_METADATA invalidations. We
do that every time we could possibly be reading new DCC/HTILE info
from the L2 cache in shaders.

Benchmark results, basemark on high preset with a navi10 on profile_standard
(which is slower than a navi10 on default settings, please don't compare
 to random navi10 results you find)

before:
  5932
  5928
  5937

after:
  6011
  6013
  6009

So this looks like a >1% increase.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
 2021-01-13 16:27:19 +00:00
Bas Nieuwenhuizen
0af86341a2 radv: Use L2 for CP DMA on GFX9+. 
This enables assuming that the L2 is always up to date for barriers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7202>
 2021-01-13 16:27:19 +00:00
Bas Nieuwenhuizen
3898f747ce radv: Use VRAM for the initial gfx cmdbuffer. 
Not expect it to make any real difference, but lets be consistent.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7979>
 2021-01-04 13:10:16 +00:00
Samuel Pitoiset
bf69d89b5a radv: implement VK_KHR_fragment_shading_rate 
Only supported on GFX10.3+. Attachment Fragment Shading Rate is
for later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7837>
 2020-12-14 16:22:38 +00:00
Samuel Pitoiset
3494551d08 radv: set the predication boolean as 32-bit if necessary 
CTS is missing tests.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7897>
 2020-12-07 09:30:05 +00:00
Samuel Pitoiset
bf36cfced1 radv: only mask 1 CU for GS/VS waves on GFX10.3 
Ported from Radeonsi and PAL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7769>
 2020-11-30 09:31:29 +00:00
Samuel Pitoiset
7729ea3d67 radv: only disable CU2 & CU3 when NGG is enabled 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7769>
 2020-11-30 09:31:29 +00:00
Marek Olšák
603b5340b9 ac: rename num_render_backends -> max_render_backends 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7542>
 2020-11-18 06:19:59 +00:00
Marek Olšák
989cc76f0c amd: replace 0x028848 with the register definition 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7264>
 2020-10-23 20:51:22 -04:00
Bas Nieuwenhuizen
78165ea3e2 radv: Record cache flushes for RGP. 
Not doing the EOP TS cacheflush event because that break wave counting
in RGP for some reason. But the rest looks to be all there.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6550>
 2020-09-28 15:46:08 +00:00
Bas Nieuwenhuizen
cc73182152 radv: Include flushes in the barrier. 
Since the flushes really happen on the next draw delay the barrier
end to include the flushes.

This fixes the barrier duration in RGP.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6550>
 2020-09-28 15:46:08 +00:00
Samuel Pitoiset
24a74b352c radv: add a tweak for PS wave CU utilization for gfx10.3 
Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6838>
 2020-09-24 10:41:21 +00:00