Before the gallium driver can support load_shader_consts_via_preamble it
needs a way to differentiate between # of API level UBOs and the number
of UBOs after the driver inserts ones for driver-params, etc. This is
because the driver UBOs are emit in a different place from user UBOs.
If we didn't have this distinction, and the app had more UBOs bound than
the shader used, we would otherwise emit some conflicting UBO
descriptors (ie. ones for unused const slots conflicting with the driver
UBO slots).
This also moves the consts_ubo emit into the PROG state.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31534>
Using address of drawable as hash table key will cause memory issue in this
situation:
1. drawable A with address addr is destroyed and deleted from the hash table.
2. drawable B with same address addr is created and added to the hash table
right after 1 is done.
3. st_framebuffers_purge will seach the hash table with drawable addr that
associated with each framebuffer. If drawable is not in the hash table, then
free this framebuffer.
So when drawable B is created, then the framebuffer that associated with
drawable A will not be freed in time. This will cause framebuffer memory leak.
Since drawable->ID is unique, this uses drawable-ID as pre-hash to store
drawable in hash table. This also removes key_hash_function because we already
use drawable-ID as pre-hash when insert the data and we need to avoid assert of
_mesa_hash_table_search_pre_hashed fail.
Signed-off-by: Julia Zhang <Julia.Zhang@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31161>
Long time ago svga had a sourceforge project where auto-generated
header files for the SVGA device were hosted. Gallium's svga driver
copied those files and when the sourceforge project became
obsolete they started being updated by hand.
Kernel and igt projects switched to the official way in which the SVGA
header files are generated but Mesa3d wasn't ported at the time.
The official SVGA headers diverged from the official ones creating bugs.
Fix it by porting the SVGA Gallium driver to the auto-generated SVGA
header files.
Signed-off-by: Zack Rusin <zack.rusin@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31653>
This will make things easier in situations where we don't want to use
the binding table at all (indirect draws/dispatches).
The mechanism is simple, upload a vec3 either through push constants
(<= Gfx12.0) or through the inline parameter register (>= Gfx12.5).
In the shader, do this :
if vec.x == 0xffffffff:
addr = pack64_2x32 vec.y, vec.z
vec = load_global addr
This works because we limit the maximum number of workgroup size to
0xffff in all dimension :
maxComputeWorkGroupCount = { 65535, 65535, 65535 },
So we can use the large values to signal the need for indirect
loading.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31508>
In SIMD32, the fence instruction is currently going to read grf0-3
leading to such assertions in the backend :
../src/intel/compiler/brw_fs_reg_allocate.cpp:206:
void fs_visitor::calculate_payload_ranges(bool, unsigned int, int*) const:
Assertion `j < payload_node_count' failed.
The reason we haven't seen the problem yet is that there always enough
payload register to accomodate this. But the following change is going
to make the inline parameter register optional.
Since SHADER_OPCODE_MEMORY_FENCE is emitted in the generator as SIMD1
NoMask (see brw_memory_fence), we can limit ourselves to SIMD1
exec_all() in the IR as well so that the IR accounts for grf0 as a
source.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31508>
These values are programmed by the kernel and not determined by the
hardware, but provide a default value that should match what drm/msm
programs for older kernels that can't report it. kgsl has always
supported returning the highest_bank_bit, although it hardcodes some of
the other parameters so we have to follow what it does instead of using
this.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26578>
