Commit Graph

53040 Commits

Author SHA1 Message Date
Stéphane Marchesin
8c28a9bd73 i915g: Don't bind 0-length programs
Since we started doing fixups for different render target formats,
this has been an issue. Instead just don't do anything, when the
program gets emitted later it'll get the correct fixup.

Fixes a bunch of piglit tests.
2012-10-04 12:39:06 -07:00
Brian Paul
91d8409649 mesa: don't call TexImage driver hooks for zero-sized images
This simply avoids some failed assertions but there's no reason to
call the driver hooks for storing a tex image if its size is zero.

Note: This is a candidate for the stable branches.
2012-10-04 07:59:11 -06:00
Rob Bradford
185d6df3c1 intel: Fix intel_texsubimage_tiled_memcpy to skip GL_EXT_unpack_subimage case
413c49141 added an optimisation to improve the performance of teximage
under a limited set of circumstances. If GL_EXT_unpack_subimage has been
used then we we must also skip this optimisation since the optimised
codepath does not take the packing values into consideration.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-10-03 16:44:22 -07:00
Matt Turner
31ab61cac1 dri drivers: Link dricommon before dynamic libraries
I think libtool should be handling this for us, but the build fails for
Jordan because libdricommon (a static library, which uses expat) appears
before -lexpat on the linker command.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Jordan Justen <jordan.l.justen@intel.com>
2012-10-03 13:41:09 -07:00
Paul Berry
551c991606 register_allocate: don't consider trivially colorable registers for spilling.
Previously, we considered all registers as candidates for spilling.
This was counterproductive--for any registers that have already been
removed from the interference graph, there is no benefit to spilling
them, since they don't contribute to register pressure.

This patch ensures that we will only try to spill registers that are
still in the interference graph after register allocation has failed.

This is consistent with the recommendations of the paper "Retargetable
Graph-Coloring Register Allocation for Irregular Architectures", on
which our register allocator is based.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-10-03 12:54:42 -07:00
Marek Olšák
53d06ecdd0 glx/dri2: use uint64_t instead of double to represent time for FPS calculation
Wine or a windows app changes fpucw to 0x7f, causing doubles to be equivalent
to floats, which broke the calculation of FPS.
We should be very careful about using doubles in Mesa.

Henri Verbeet adds:
  For reference, this is done by for example d3d9 when a D3D device is
  created without D3DCREATE_FPU_PRESERVE set. In the general case
  applications can do all kinds of terrible things to the FPU control
  word of course.
2012-10-03 16:55:48 +02:00
Oliver McFadden
ff835724b5 mesa: tests: EnumStrings.LookUpByNumber
[ RUN      ] EnumStrings.LookUpByNumber
enum_strings.cpp:43: Failure
Value of: _mesa_lookup_enum_by_nr(everything[i].value)
  Actual: "GL_COMPRESSED_RGBA_S3TC_DXT3_ANGLE"
Expected: everything[i].name
Which is: "GL_COMPRESSED_RGBA_S3TC_DXT3_EXT"
enum_strings.cpp:43: Failure
Value of: _mesa_lookup_enum_by_nr(everything[i].value)
  Actual: "GL_COMPRESSED_RGBA_S3TC_DXT5_ANGLE"
Expected: everything[i].name
Which is: "GL_COMPRESSED_RGBA_S3TC_DXT5_EXT"
[  FAILED  ] EnumStrings.LookUpByNumber (2 ms)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55505
Signed-off-by: Oliver McFadden <oliver.mcfadden@linux.intel.com>
2012-10-03 14:11:58 +03:00
Andreas Boll
336cc6499b docs: add link to the GLSL compiler page
This reverts commit 9e0931e355

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-10-03 08:54:12 +02:00
Andreas Boll
d495669965 docs: update shading documentation
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-10-03 08:53:46 +02:00
Matt Turner
159ca32fec build: Remove autoconf check for signbit
rebase failure in 7da12426f7.
2012-10-02 22:50:02 -07:00
Stéphane Marchesin
fe3aeb7ea3 i915g: Implement srgb textures the easy way.
Since the hw can do it, let's use the hw. It's less accurate
but doesn't have the shader instruction count shortcomings.
2012-10-02 17:54:50 -07:00
Stéphane Marchesin
2acc719374 i915g: Use X tiling for textures
This is what the classic driver does, and it allows faster
texture uploads.
2012-10-02 17:54:48 -07:00
Robert Bragg
0a523a8820 SwapBuffersRegionNOK: invert rectangles on y axis
The EGL_NOK_swap_region2 spec states that the rectangles are specified
with a bottom-left origin within a surface coordinate space also with a
bottom left origin, so this patch ensures the rectangles are flipped
before passing them on to dri2_copy_region.

Fixes piglit's egl-nok-swap-region test.

Tested-by: Matt Turner <mattst88@gmail.com>
2012-10-02 14:49:00 -07:00
Brian Paul
df4a88ac43 mesa: remove bogus compressed texture size checks
A compressed texture image size doesn't have to be a multiple of the
compressed block size (only sub-images do).  Fixes issues when building
compressed mipmaps because we often wind up with non-block-size images
for the higher mipmap levels.

Fixes https://bugs.freedesktop.org/show_bug.cgi?id=55445

Note: This is a candidate for the stable branches.

Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Sven Arvidsson <sa@whiz.se>
2012-10-02 15:19:00 -06:00
Michel Dänzer
82e38ac91f radeonsi: Fix double compilation of shader variants.
Fixes crash in piglit glsl-max-varyings.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-02 17:53:47 +02:00
Michel Dänzer
c3db19efba radeonsi: Better indexing of parameters in the pixel shader.
We were previously using the TGSI input index, which can exceed the number of
parameters passed from the vertex shader via the parameter cache. Now we use
a separate index which only counts those parameters.

Prevents piglit regressions with the following fix.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-02 17:50:58 +02:00
Michel Dänzer
dbb4a7f950 radeon/llvm: Disable SI flow control again for now.
It makes piglit unreliable due to VM protection faults and GPU lockups.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-10-02 16:50:36 +02:00
Andreas Boll
48e4eb695a docs/helpwanted: cleanup todo list links
split into common and driver specific To-Do lists
add an explanation for each To-Do list

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-10-02 15:44:34 +02:00
Andreas Boll
1f38fb2697 docs: document how to apply a candidate to a stable branch
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-10-02 15:44:28 +02:00
Andreas Boll
f07784d9ba docs: document how to mark a candidate for a stable branch
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-10-02 15:44:00 +02:00
Negreanu Marius Adrian
e00abb00f0 android: glcpp: fix abuse of yylex
Port the 'glcpp: fix abuse of yylex' commit to Android.mk
Also, since the Android.*.mk are sourced in a global namespace,
the local-y-to-c-and-h is prefixed with the LOCAL_MODULE name,

The initial fix commit is 53d46bc787

There's also a bugzilla for this: 54947

Signed-off-by: Negreanu Marius Adrian <adrian.m.negreanu@intel.com>
Reviewed-by: Oliver McFadden <oliver.mcfadden@linux.intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2012-10-02 08:14:34 +03:00
Matt Turner
523c015246 build: Don't build libdricore if not building classic drivers 2012-10-01 15:23:05 -07:00
Matt Turner
b6c0fa1280 libdricore: Remove dead C(XX)FLAGS_NOVISIBILITY 2012-10-01 15:23:05 -07:00
Matt Turner
24ded89876 build: Add visibility CFLAGS to OSMesa 2012-10-01 15:23:05 -07:00
Matt Turner
1762ec28db build: Link OSMesa with glapi, libdl, libstdc++
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=399813
          https://bugs.freedesktop.org/show_bug.cgi?id=53179
2012-10-01 15:23:05 -07:00
Matt Turner
4cfff7211c build: Set visibility CFLAGS in dri/swrast 2012-10-01 15:23:05 -07:00
Matt Turner
3628402707 build: Set visibility CFLAGS in dri/r200 2012-10-01 15:23:05 -07:00
Matt Turner
55d45efdd8 build: Set visibility CFLAGS in dri/radeon 2012-10-01 15:23:05 -07:00
Matt Turner
340637d54d build: Set visibility CFLAGS in dri/nouveau 2012-10-01 15:23:04 -07:00
Matt Turner
381d120b8a build: Set visibility CFLAGS in dri/i915 2012-10-01 15:23:04 -07:00
Matt Turner
d2872b5612 build: Set visibility CFLAGS in dri/common 2012-10-01 15:23:04 -07:00
Matt Turner
8746f641bb build: Build src/glsl with visibility CFLAGS 2012-10-01 15:23:04 -07:00
Matt Turner
710a90ccaf build: Turn on visibility CFLAGS for core mesa 2012-10-01 15:23:04 -07:00
Matt Turner
63c3a051cd build: Order src/Makefile correctly 2012-10-01 15:23:04 -07:00
Matt Turner
814345f54b build: Use AX_PTHREAD's HAVE_PTHREAD preprocessor definition 2012-10-01 15:23:04 -07:00
Matt Turner
b6651ae6ad build: Use PTHREAD_LIBS and PTHREAD_CFLAGS 2012-10-01 15:23:04 -07:00
Matt Turner
dd4fde8f67 build: Set PTHREAD_LIBS for pkgconfig files if empty 2012-10-01 15:20:50 -07:00
Tom Stellard
00d80b3a6f llvmpipe: Fix build with LLVM 2.8
Commit 8d9778589f added all-targets to the
LLVM_COMPONENTS list, but this component does not exist with LLVM 2.8.

Adding all-targets is not necessary for any drivers, and it seems to be
left over from earlier versions of the commit mentioned above.

Tested-by: Stéphane Marchesin <marcheu@chromium.org>
2012-10-01 17:42:56 -04:00
Tom Stellard
67fcb3c2b4 configure.ac: Use amdgpu component for LLVM 3.2
The amdgpu component actually does exist.  I must have been using an
older version of llvm-config by accident when I first made this change.
2012-10-01 21:14:10 +00:00
Tom Stellard
f2f17fc348 radeon/llvm: Only initialize the AMDGPU target 2012-10-01 21:14:10 +00:00
Tom Stellard
cbd09a9e5c radeon: Fix build with LLVM 3.1
The build was broken by commit 8d9778589f
2012-10-01 15:47:31 -04:00
Tom Stellard
8d9778589f radeon: Support LLVM 3.2
LLVM 3.2 and newer requires that the R600/SI backend be part of the
LLVM tree.
2012-10-01 15:37:17 +00:00
Tom Stellard
91ee735001 r600g: Re-enable growing of the compute memory pool 2012-10-01 15:37:16 +00:00
Tom Stellard
44b1050e6c r600g: Fix bug when adding new items to the compute memory pool
The items are ordered in the item list by their offsets, with the lowest
offset coming first in the list.  The old code was assuming that new
items being added to the list would always have a greater offset than
the first item in the list, however this is not always the case.
2012-10-01 15:37:16 +00:00
Tom Stellard
eacca90f43 r600g: Use a RAT buffer as the backing bo for the compute memory pool 2012-10-01 15:37:16 +00:00
Tom Stellard
5cd1c65dc1 r600g: Make sure to init the compute memory pool with enough memory 2012-10-01 15:37:16 +00:00
Tom Stellard
2508d43c36 r600g: Add evergreen_init_color_surface_rat() v2
This can be used to initialize the CB* registers for buffers without a
radeon_surface.

v2:
  - Get correct group_bytes value from r600_screen
  - Stop setting unnecessary fields

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-10-01 15:37:16 +00:00
Tom Stellard
d13c3b19f9 r600g: Add register field definitions for 028C70_RESOURCE_TYPE
Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-10-01 15:37:16 +00:00
Oliver McFadden
9545d9611f intel: add support for ANGLE_texture_compression_dxt.
Signed-off-by: Oliver McFadden <oliver.mcfadden@linux.intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-10-01 17:21:51 +03:00
Alex Deucher
304beb81bb radeonsi: emit PA_SU_PRIM_FILTER_CNTL
has no default value.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <deathsimple@vodafone.de>
2012-10-01 10:29:51 +02:00