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Author SHA1 Message Date
Samuel Pitoiset
8ba1860fbd radv: add a new shader argument for non-monolithic shaders PC 
This will be used to jump from VS to TCS/GS or TES to GS on GFX9+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
 2023-08-25 07:22:03 +00:00
Samuel Pitoiset
7b4f10b434 radv: always declare some arguments for non-monolithic VS/TCS shaders 
For separate VS/TCS compilation on GFX9+, the TCS might be using push
constants but not the VS and we can't know this information when
compiling the VS. Similar logic for the other arguments.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
 2023-08-25 07:22:03 +00:00
Samuel Pitoiset
a4933d2d7f radv: force indirect descriptor sets for non-monolithic shaders 
When VS and TCS are compiled separately on GFX9+, we can't know how
many descriptor sets are used for both stages and the function
arguments must match.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
 2023-08-25 07:22:03 +00:00
Samuel Pitoiset
e5d30462c9 radv: do not inline push constants for non-monolithic shaders 
It's hard to implement this because the function arguments must match
when eg. VS or TCS are compiled separately on GFX9+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
 2023-08-25 07:22:03 +00:00
Samuel Pitoiset
34ddde6d63 radv: use info->uses_view_index directly when declaring shader arguments 
No need for a separate variable.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
 2023-08-25 07:22:03 +00:00
Samuel Pitoiset
467bf47281 radv: add radv_shader_info::is_monolithic 
This will be used to implement shader object on GFX9+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24697>
 2023-08-25 07:22:03 +00:00
Benjamin Cheng
f64f08a9e0 anv/video: send h264 scaling list in raster order 
ITU spec defines the H264 ScalingList{4x4,8x8} in zig-zag order, but
Intel HW wants raster order.

Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24572>
 2023-08-25 03:08:13 +00:00
Benjamin Cheng
dd20ec5655 radv/video: send h264 scaling list in raster order 
ITU spec defines the H264 ScalingList{4x4,8x8} in zig-zag order, but
AMD HW wants raster order.

Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24572>
 2023-08-25 03:08:13 +00:00
Benjamin Cheng
1d2f7f068c util/vl: extract gallium vl scanning data to shared code 
Vulkan video on both ANV and RADV need these data to make converting
from zig-zag to raster order easier.

Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24572>
 2023-08-25 03:08:13 +00:00
Benjamin Cheng
e921b889e3 anv/video: use vk_video_derive_h264_scaling_list 
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24572>
 2023-08-25 03:08:13 +00:00
Benjamin Cheng
d578e4416a radv/video: use vk_video_derive_h264_scaling_list 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24572>
 2023-08-25 03:08:13 +00:00
Benjamin Cheng
8daa329634 vulkan/video: add helper to derive H264 scaling lists 
The H264 spec defines a complicated way of layering PPS scaling lists
on top of SPS scaling lists. The details can be found in 7.4.2.1
(seq_scaling_matrix_present_flag semantics) and 7.4.2.2
(pic_scaling_matrix_present_flag semantics).

Both ANV and RADV need to derive the final scaling lists sent to HW
using this logic in order to handle H264 scaling lists correctly.

Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24572>
 2023-08-25 03:08:13 +00:00
Yiwei Zhang
0d4df682b9 venus: add no_sparse debug option to disable sparse resource support 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24877>
 2023-08-25 01:12:29 +00:00
twisted89
d3e796da6b util/driconf: add workarounds for the Chronicles of Riddick 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24567>
 2023-08-24 22:38:56 +00:00
Mike Blumenkrantz
640173cdbb zink: fix rewrite_read_as_0 filtering 
Fixes: 9e42553ca8 ("zink: use lowered io (kinda) for i/o vars")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24874>
 2023-08-24 21:27:50 +00:00
Faith Ekstrand
f9cf872745 nouveau/mme: Fix a compile warning 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24840>
 2023-08-24 19:26:44 +00:00
Faith Ekstrand
819d359d1d nvk: Plumb no_prefetch through to the DRM back-end 
Instead of using bit 23 of nvk_cmd_push::range for this, pass it as a
separate bool.  This lets us use the actual kernel flag with the new
UAPI.

Reviewed-by: Danilo Krummrich <dakr@redhat.com>
Tested-by: Danilo Krummrich <dakr@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24840>
 2023-08-24 19:26:44 +00:00
Faith Ekstrand
458baeee5f drm-uapi: Sync nouveau_drm.h 
From https://cgit.freedesktop.org/drm-misc/

    commit 443f9e0b1ab5e3b95abf8606097d13e30e2f2413
    Author: Danilo Krummrich <dakr@redhat.com>
    Date:   Wed Aug 23 20:15:34 2023 +0200

        drm/nouveau: uapi: don't pass NO_PREFETCH flag implicitl

Reviewed-by: Danilo Krummrich <dakr@redhat.com>
Tested-by: Danilo Krummrich <dakr@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24840>
 2023-08-24 19:26:44 +00:00
Ian Romanick
8852e9cb2e util/rb-tree: Fix typo in comment 
Trivial.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24856>
 2023-08-24 17:50:28 +00:00
Ian Romanick
2ff38260b9 util/rb-tree: Return the actual first node from rb_tree_search 
Previously rb_tree_search would return the first node encountered, but
that may not be the first node that would be encoutnered by, say,
rb_tree_foreach.

Two test cases are added.

v2: Add more curly braces. Suggested by Faith.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24856>
 2023-08-24 17:50:28 +00:00
David Heidelberg
e51056f9f7 ci/iris: add GL46.arrays_of_arrays_gl.SizedDeclarationsPrimitive timeout 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24870>
 2023-08-24 17:06:42 +00:00
Dmitry Baryshkov
2fdcc00b01 tu: Pass real size of prime buffers to allocator 
The msm driver reserves the actual DMABUF size in the memory map, while
TU can request smaller memory chunk to be allocated. This potentially
can lead to a situation when next allocation IOVA will be in the middle
of the address space which is reserved for the DMABUF. Pass the
`real_size' to TU allocator instead, so that kernel and userspace have
the same picture of memory allocations.

Cc: mesa-stable
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24861>
 2023-08-24 16:35:43 +00:00
Alyssa Rosenzweig
cda1961835 treewide: Also handle struct nir_builder form 
Via Coccinelle patch:

    @def@
    typedef bool;
    typedef nir_builder;
    typedef nir_instr;
    typedef nir_def;
    identifier fn, instr, intr, x, builder, data;
    @@

    static fn(struct nir_builder* builder,
    -nir_instr *instr,
    +nir_intrinsic_instr *intr,
    ...)
    {
    (
    -   if (instr->type != nir_instr_type_intrinsic)
    -      return false;
    -   nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
    |
    -   nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
    -   if (instr->type != nir_instr_type_intrinsic)
    -      return false;
    )

    <...
    (
    -instr->x
    +intr->instr.x
    |
    -instr
    +&intr->instr
    )
    ...>

    }

    @pass depends on def@
    identifier def.fn;
    expression shader, progress;
    @@

    (
    -nir_shader_instructions_pass(shader, fn,
    +nir_shader_intrinsics_pass(shader, fn,
    ...)
    |
    -NIR_PASS_V(shader, nir_shader_instructions_pass, fn,
    +NIR_PASS_V(shader, nir_shader_intrinsics_pass, fn,
    ...)
    |
    -NIR_PASS(progress, shader, nir_shader_instructions_pass, fn,
    +NIR_PASS(progress, shader, nir_shader_intrinsics_pass, fn,
    ...)
    )

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24852>
 2023-08-24 15:48:02 +00:00
Alyssa Rosenzweig
465b138f01 treewide: Use nir_shader_intrinsic_pass sometimes 
This converts a lot of trivial passes. Nice boilerplate deletion. Via Coccinelle
patch (with a small manual fix-up for panfrost where coccinelle got confused by
genxml + ninja clang-format squashed in, and for Zink because my semantic patch
was slightly buggy).

    @def@
    typedef bool;
    typedef nir_builder;
    typedef nir_instr;
    typedef nir_def;
    identifier fn, instr, intr, x, builder, data;
    @@

    static fn(nir_builder* builder,
    -nir_instr *instr,
    +nir_intrinsic_instr *intr,
    ...)
    {
    (
    -   if (instr->type != nir_instr_type_intrinsic)
    -      return false;
    -   nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
    |
    -   nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
    -   if (instr->type != nir_instr_type_intrinsic)
    -      return false;
    )

    <...
    (
    -instr->x
    +intr->instr.x
    |
    -instr
    +&intr->instr
    )
    ...>

    }

    @pass depends on def@
    identifier def.fn;
    expression shader, progress;
    @@

    (
    -nir_shader_instructions_pass(shader, fn,
    +nir_shader_intrinsics_pass(shader, fn,
    ...)
    |
    -NIR_PASS_V(shader, nir_shader_instructions_pass, fn,
    +NIR_PASS_V(shader, nir_shader_intrinsics_pass, fn,
    ...)
    |
    -NIR_PASS(progress, shader, nir_shader_instructions_pass, fn,
    +NIR_PASS(progress, shader, nir_shader_intrinsics_pass, fn,
    ...)
    )

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24852>
 2023-08-24 15:48:02 +00:00
David Heidelberg
5fa9f842b0 ci: switch to 6.4 kernel, improving Adreno 660 reliability 
Second argument is to leave Linux 6.3 which is EOL.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24815>
 2023-08-24 13:12:28 +00:00
David Heidelberg
39a0791627 ci/freedreno: There is only one King of Town. 
Drop -r1, which got removed in the Linux 6.4.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24815>
 2023-08-24 13:12:28 +00:00
David Heidelberg
fd21c998e6 ci/piglit: add extra space on top to prevent single quote getting into URL 
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24815>
 2023-08-24 13:12:28 +00:00
Karol Herbst
9c3746fe9c zink: update some compute caps 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24859>
 2023-08-24 12:44:23 +00:00
Karol Herbst
ac289b7268 zink: fix global stores 
We have to cast the value if the type doesn't match.

Fixes: ddc5c30489 ("zink: handle global and scratch vars")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24859>
 2023-08-24 12:44:23 +00:00
Karol Herbst
ac1685bc6a zink: fix source type in load/store scratch 
Fixes: ddc5c30489 ("zink: handle global and scratch vars")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24859>
 2023-08-24 12:44:23 +00:00
Mike Blumenkrantz
db41d62be9 zink: use Aligned with global load/store ops 
this is required by spec

Fixes: ddc5c30489 ("zink: handle global and scratch vars")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24859>
 2023-08-24 12:44:22 +00:00
Mike Blumenkrantz
2ff560514b zink: handle global atomic intrinsics 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24859>
 2023-08-24 12:44:22 +00:00
Mauro Rossi
ef6725a5f4 hasvk/android: remove numFds check 
Change required for compatibility with minigbm gralloc4
due to gralloc handle having DRV_MAX_FDS = (DRV_MAX_PLANES + 1)

https://android.googlesource.com/platform/external/minigbm/+/refs/tags/android-13.0.0_r18/cros_gralloc/cros_gralloc_handle.h#14

Cc: "22.3" mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7807
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20231>
 2023-08-24 11:07:12 +00:00
Mauro Rossi
143d417fcc anv/android: remove numFds check 
Change required for compatibility with minigbm gralloc4
due to gralloc handle having DRV_MAX_FDS = (DRV_MAX_PLANES + 1)

https://android.googlesource.com/platform/external/minigbm/+/refs/tags/android-13.0.0_r18/cros_gralloc/cros_gralloc_handle.h#14

Cc: "22.2" "22.3" mesa-stable
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20231>
 2023-08-24 11:07:12 +00:00
Chris Spencer
6a4e9b55e4 anv: Don't reject Android image format if external props not supplied 
anv_GetPhysicalDeviceImageFormatProperties2 returns 'not supported' if an
Android hardware buffer external memory handle type is specified, but no
external image format properties output struct is supplied. This struct is
optional, so we should populate it if present, but return successfully
either way.

This fixes an error when using ANV with hwui, which otherwise prevents the
system from booting.[1]

[1] https://cs.android.com/android/platform/superproject/main/+/main:frameworks/base/libs/hwui/renderthread/VulkanSurface.cpp;l=271;drc=ad3fb95aa2fe0be59d3e991ddc883592ab5542bc

Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24844>
 2023-08-24 10:26:09 +00:00
Simon Ser
5ceba97c2e vulkan/wsi/wayland: add support for IMMEDIATE 
Use the tearing-control-unstable-v1 protocol to indicate to the
Wayland compositor that tearing is acceptable.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18268>
 2023-08-24 09:38:54 +00:00
Simon Ser
f7da5e3e38 wayland: enable use of wayland-protocols as a subproject 
This allows developers to link subprojects/wayland-protocols/ to
a repository checkout. Useful when adding support for new protocols.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18268>
 2023-08-24 09:38:53 +00:00
Jordan Justen
d65b0b0424 intel/dev: Add more RPL PCI IDs 
Ref: https://patchwork.freedesktop.org/patch/553646/?series=122712&rev=1
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24820>
 2023-08-24 00:42:19 -07:00
Jordan Justen
27f6b4b1c6 intel/dev: Use RPL-U name on RPL-U devices 
Ref: https://patchwork.freedesktop.org/patch/553646/?series=122712&rev=1
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24820>
 2023-08-24 00:42:19 -07:00
Samuel Pitoiset
112b393766 radv: stop declaring unused SGPR arguments for PS epilogs 
ACO no longer requires these arguments.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24838>
 2023-08-24 07:21:58 +00:00
Samuel Pitoiset
0004d903d4 radv: fix the per-patch data offset when TES isn't linked with TCS 
When TCS and TES aren't linked together and TCS exports unused outputs,
the per-patch data offset needs to be adjusted. This is similar to the
LS-HS vertex stride when VS and TCS aren't linked together.

This fixes a bunch of failures by forcing the driver to use TCS epilogs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24776>
 2023-08-24 06:03:12 +00:00
Tapani Pälli
d65fe6eff1 mesa: fix some TexParameter and SamplerParameter cases 
EXT extension was added without tests so these functions did
not work properly.

Fixes: 799710be88 ("mesa: Add EXT_texture_mirror_clamp_to_edge to extension table")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24845>
 2023-08-24 04:26:52 +00:00
Yonggang Luo
26c5200acf compiler/glsl: Move glsl_print_type from glsl_types.* to ir_print_visitor.cpp 
glsl_print_type only referenced in ir_print_visitor.cpp
there is no need expose it

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24824>
 2023-08-24 02:54:09 +00:00
Yonggang Luo
01ddb18427 compiler: use 4 instead ATOMIC_COUNTER_SIZE in glsl_types.h to avoid #include "mesa/main/config.h" 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24824>
 2023-08-24 02:54:09 +00:00
Yonggang Luo
26a23a7c1f d3d12: replace use of MAX_VERTEX_STREAMS with PIPE_MAX_VERTEX_STREAMS 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24824>
 2023-08-24 02:54:09 +00:00
Yonggang Luo
0b84e38684 intel/brw: use 4 instead of MAX_VERTEX_STREAMS to avoid #include "mesa/main/config.h" 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24824>
 2023-08-24 02:54:08 +00:00
Yonggang Luo
d6f8bdcb5f sfn: Use 4 instead of ATOMIC_COUNTER_SIZE 
../../src/gallium/drivers/r600/sfn/sfn_nir.cpp:458:59: error: ‘ATOMIC_COUNTER_SIZE’ was not declared in this scope

../../src/gallium/drivers/r600/sfn/sfn_shader.cpp:609:53: error: ‘ATOMIC_COUNTER_SIZE’ was not declared in this scope

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24824>
 2023-08-24 02:54:08 +00:00
Rob Clark
75789e9429 tu: Workaround bionic _SC_LEVEL1_DCACHE_LINESIZE 
Bionic just returns a hard-coded 0, which isn't helpful.  But
fortunately on aarch64 it is easy enough just to read the value
ourselves.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24829>
 2023-08-23 22:41:55 +00:00
Kenneth Graunke
08fc4603dd intel/fs: Dump IR for pre-RA scheduler modes in DEBUG_OPTIMIZER 
This lets us more easily compare and contrast the various scheduling
options that the compiler considered.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24707>
 2023-08-23 21:34:38 +00:00
Kenneth Graunke
07f2ad32e4 intel/fs: Pick the lowest register pressure schedule when spilling 
We try various pre-RA scheduler modes and see if any of them allow
us to register allocate without spilling.  If all of them spill,
however, we left it on the last mode: LIFO.  This is unfortunately
sometimes significantly worse than other modes (such as "none").

This patch makes us instead select the pre-RA scheduling mode that
gives the lowest register pressure estimate, if none of them manage
to avoid spilling.  The hope is that this scheduling will spill the
least out of all of them.

fossil-db stats (on Alchemist) speak for themselves:

    Totals:
    Instrs: 197297092 -> 195326552 (-1.00%); split: -1.02%, +0.03%
    Cycles: 14291286956 -> 14303502596 (+0.09%); split: -0.55%, +0.64%
    Spill count: 190886 -> 129204 (-32.31%); split: -33.01%, +0.70%
    Fill count: 361408 -> 225038 (-37.73%); split: -39.17%, +1.43%
    Scratch Memory Size: 12935168 -> 10868736 (-15.98%); split: -16.08%, +0.10%

    Totals from 1791 (0.27% of 668386) affected shaders:
    Instrs: 7628929 -> 5658389 (-25.83%); split: -26.50%, +0.67%
    Cycles: 719326691 -> 731542331 (+1.70%); split: -10.95%, +12.65%
    Spill count: 110627 -> 48945 (-55.76%); split: -56.96%, +1.20%
    Fill count: 221560 -> 85190 (-61.55%); split: -63.89%, +2.34%
    Scratch Memory Size: 4471808 -> 2405376 (-46.21%); split: -46.51%, +0.30%

Improves performance when using XeSS in Cyberpunk 2077 by 90% on A770.
Improves performance of Borderlands 3 by 1.54% on A770.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24707>
 2023-08-23 21:34:38 +00:00