OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
184,340 Commits 9 Branches 1 Tag
8a05cb8da70310d2ba76a48f1a3d892b9aecb41b
Commit Graph

184340 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Samuel Pitoiset
90e354afb0 radv: determine the workgroup size for GS non-NGG earlier 
The wavesize for VS/TES/GS is always the same, so this can be computed
earlier.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27431>
 2024-02-06 20:12:38 +00:00
Samuel Pitoiset
35c9631162 radv: determine the ES stage earlier when processing binary config 
This will help implementing VS+GS and TES+GS compiled separately on
GFX9+ because the shader config will need to be combined.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27431>
 2024-02-06 20:12:38 +00:00
Samuel Pitoiset
03314b2a86 radv: check for MESA_SHADER_TESS_EVAL in radv_fill_shader_info_ngg() 
This seems clearer to me.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27470>
 2024-02-06 19:53:24 +00:00
Samuel Pitoiset
34572d535e radv: use next_stage to determine the NGG stage 
This shouldn't change anything, except that it will help for ESO.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27470>
 2024-02-06 19:53:24 +00:00
Samuel Pitoiset
31f006d352 radv: always set GS as NGG if present on GFX11 
GFX11 is full NGG.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27470>
 2024-02-06 19:53:24 +00:00
Samuel Pitoiset
55093270ed radv: squash GFX10/GFX10.3 NGG restrictions in the same condition 
They don't apply on GFX11.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27470>
 2024-02-06 19:53:24 +00:00
Samuel Pitoiset
237ab5db86 radv: remove one indentation level in radv_fill_shader_info_ngg() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27470>
 2024-02-06 19:53:24 +00:00
David Heidelberg
010272b62e util: use crc32_z instead of crc32 and bump zlib dep to 1.2.9 
1.2.9 has been released in January 2017, so let's assume
we'll find it everywhere.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27311>
 2024-02-06 19:22:53 +00:00
David Heidelberg
56f31d1847 meson: upgrade zlib wrap to 1.3.1 
`$ meson wrap update zlib`

Cc: mesa-stable
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27311>
 2024-02-06 19:22:53 +00:00
Pavel Ondračka
238c3d593b r300/ci: update piglit fails 
Most likely changed by recent piglit uprev.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27493>
 2024-02-06 17:32:13 +00:00
Eric Engestrom
f9acd9e659 v3dv/ci: test the WSI on rpi4 and rpi5 
Add a few tests to the skip list because they take over a minute to finish.

All the other new tests run in less than 50 seconds.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27315>
 2024-02-06 17:15:07 +00:00
Christian Gmeiner
7c198d4404 isaspec: encode.py: Include assert.h 
pack_field(..) makes use of assert(..).

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27491>
 2024-02-06 16:38:01 +00:00
Zan Dobersek
c3b667d488 tu/msm: fix RD_CHIP_ID size used when dumping RD 
The chip ID field size is 8 bytes across fd_dev_id and different RD tools.
The call to fd_rd_output_write_section for RD_CHIP_ID should be fixed to
use the proper size as well.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27430>
 2024-02-06 16:01:20 +00:00
Rhys Perry
4f6aac1589 aco/tests: fix to_hw_instr.swap_linear_vgpr 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27436>
 2024-02-06 15:40:58 +00:00
Rhys Perry
174e37afb9 aco: fix >8 byte linear vgpr copies 
No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27436>
 2024-02-06 15:40:58 +00:00
Hsieh, Mike
33d88f797b amd/vpelib: Add UID for 3d Lut and control logic 
[WHY]
3D lut generation takes time, we need to cache it and identify it as it
updated.

[HOW]
Add unique id when new 3d lut is generated.
Add control logic with UID.

Reviewed-by: Jesse Agate <jesse.agate@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27239>
 2024-02-06 14:55:02 +00:00
Agate, Jesse
039b1e0a1e amd/vpelib: Refactor norm factor logic 
Moved norm factor logic out of moveable CM.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Jesse Agate <Jesse.Agate@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27239>
 2024-02-06 14:55:02 +00:00
Shih, Jude
e0863dbb74 amd/vpelib: Solve link error due to missing static for one function 
is_target_rect_equal_to_dest_rect is used in color_bg.c only. Therefore,
it needs keyword as static in front of it. This issue is reported from
diag team.

Reviewed-by: Bichao Wang <bichao.wang@amd.com>
Reviewed-by: Tomson Chang <tomson.chang@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Jude Shih <shenshih@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27239>
 2024-02-06 14:55:02 +00:00
Agate, Jesse
2d02c75324 amd/vpelib: Add PQ Norm to VPE interface 
Rename the variable and add PQ Norm to VPE interaface.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Jesse Agate <Jesse.Agate@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27239>
 2024-02-06 14:55:02 +00:00
Agate, Jesse
1dd28d6766 amd/vpelib: VPE integration for HLG 
Added external and internal enums for HLG and some related house keeping.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Jesse Agate <Jesse.Agate@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27239>
 2024-02-06 14:55:02 +00:00
Hsieh, Mike
5fd59c83ef amd/vpelib: geometric scaling fix 
[WHY & HOW]
Color adjustment needs to be controled by user.
Remove blending check if target rect equeal to dest rect for 1st stream.

Reviewed-by: Tomson Chang <tomson.chang@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27239>
 2024-02-06 14:55:02 +00:00
Hsieh, Mike
c8b2e28b66 amd/vpelib: skip gamma remap and cs conversion when geometric scaling 
[WHY]
When geomtric scaling is enabled, many color features will be skipped.

[HOW]
Skip gamma remap, gamut conversion, blending, tone mapping and color adjustment.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27239>
 2024-02-06 14:55:02 +00:00
Mike Hsieh
cb6d928327 amd/vpelib: Add param check for geometric scaling and refactor 
[WHY]
Param check for geometric scaling is required.
3dlut for geometric scaling case is too complicate.

[HOW]
Add Param check for geometric scaling.
Refactor 3dlut for geometric scaling case.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27239>
 2024-02-06 14:55:02 +00:00
Hsieh, Mike
4893afd427 amd/vpelib: add new tf enum and add flag for geometric scaling 
[WHY] 1. Need tf enum for SRGB and BT709
      2. Add required flag and logic for geometric scaling

[HOW] Add new enum, skip tone mapping when geometric scaling is enabled

Reviewed-by: Jesse Agate <jesse.agate@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27239>
 2024-02-06 14:55:02 +00:00
Juan A. Suarez Romero
31c9e17bf2 v3d/ci: update expected list 
Add new piglit failure

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27484>
 2024-02-06 13:33:39 +00:00
Samuel Pitoiset
d15a43c9a9 radv: limit maxIndirectCommandsTokenCount to 512 
512 is already large enough but UIN32_MAX is definitely too large.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27466>
 2024-02-06 11:23:29 +00:00
Sviatoslav Peleshko
0a44f6319e anv,driconf: Add sampler coordinate precision workaround for AoE 4 
AoE4 samples texture on the edge between texels, which can cause
unexpected texel to be returned, and cause misrenderings. This workaround
enables coordinate rounding even in NEAREST mode, which fixes the problem.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9864
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27337>
 2024-02-06 10:29:15 +00:00
Juston Li
e48645250c venus: image format properties cache 
Cache for vkGetPhysicalDeviceImageFormatProperties2 as it is observed
to be called repeatedly with zink/proton layers.

Cache design is the same as the image requirements cache, generating
a hash key from pImageFormatInfo and storing pImageFormatProperties
into a hash table.

There are a couple differences though:
- VkResult gets cached when the query returns NOT_SUPPORTED.
- Unlike pMemoryRequirements that returns VkMemoryRequirements2 and
possibly VkMemoryDedicatedRequirements, VkImageFormatProperties2
has various pNext chains that can be optionally passed in. Hash
the existence of these pNext so that they are considered different
queries and the underlying pNext struct can be optionally cached.
The alternative would be to modify the query to always chain these
pNext so all of them would be cached, but it is unlikely for queries
to only differ in pNext chains.

Signed-off-by: Juston Li <justonli@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27401>
 2024-02-06 00:26:45 +00:00
Juston Li
680c912977 venus: extract cache hash/equals functions into common 
drop the unnecessary casting in the equals function as well

Signed-off-by: Juston Li <justonli@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27401>
 2024-02-06 00:26:45 +00:00
Juston Li
f3de6f17c1 venus: fix image reqs cache store locking 
lock the entire scope when storing image reqs cache entry to prevent
entry being added between the split locks.

Fixes: b51ff22fbe ("venus: support caching image memory requirements")

Signed-off-by: Juston Li <justonli@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27401>
 2024-02-06 00:26:44 +00:00
Tapani Pälli
5178ad761c anv: flush tile cache independent of format with HIZ-CCS flush 
Cc: mesa-stable
Fixes: ba87656079 ("anv: implement undocumented tile cache flush requirements")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10420
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10530
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27440>
 2024-02-05 21:50:26 +00:00
Mike Blumenkrantz
af51e5f7a9 zink: split out sparse_residency_code_and lowering 
the lowering for is_sparse_texels_resident must run after all the instances of
sparse_residency_code_and have been eliminated in order to effectively guarantee
that there are no remaining cases of tex.e (sparse) component access

fixes #10548

Fixes: f0ca477b500 ("zink: run sparse lowering after all optimization passes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27474>
 2024-02-05 21:28:47 +00:00
Mike Blumenkrantz
f5174593c1 zink: add back (safe) optimizations after sparse lowering 
this cleans up the sparse_residency_code_and disaster

Fixes: f0ca477b500 ("zink: run sparse lowering after all optimization passes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27474>
 2024-02-05 21:28:47 +00:00
Caio Oliveira
40d119979a iris: Remove unused paramater 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27476>
 2024-02-05 21:07:20 +00:00
Caio Oliveira
a4dc5bd9fd iris: Remove prototypes for unsupported Gfx versions 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27476>
 2024-02-05 21:07:20 +00:00
Caio Oliveira
8ff26271a7 iris: Remove unused brw_* includes 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27476>
 2024-02-05 21:07:20 +00:00
Friedrich Vock
d4c094dfb4 radv/rt: Optimize update shader VGPR usage 
Brings VGPR allocation down from 72 (absolutely insane) to 32.

We can now reach the theoretical maximum occupancy of 16 waves per SIMD.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27472>
 2024-02-05 21:14:45 +01:00
Max R
585836f2b5 d3d10umd: Rename d3d10sw target to d3d10umd 
Other drivers such as virgl are planned to be added to d3d10... target.
As it is not a purely software driver d3d10sw target is renamed to
d3d10umd target to reflect that.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27416>
 2024-02-05 16:59:22 +00:00
Max R
67da5a8f08 d3d10umd, meson: Allow naming d3d10umd DLLs 
For graphics drivers on windows it is beneficial to have usermode DLLs
names matching driver overall name, example being vm3dum_10.dll and
nvwgf2um.dll for d3d10 usermode drivers from VMWare and Nvidia.

To implement that new meson option `gallium-d3d10-dll-name` that
names the resulting d3d10umd target DLL is introduced. Additionaly,
to avoid confusion `gallium-dll-name` is renamed to `gallium-wgl-dll-name`
as it corresponds to the name used in wgl target.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27416>
 2024-02-05 16:59:22 +00:00
Tapani Pälli
5ae2b4882a blorp: implement Wa_16014912113 callback for drivers 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26920>
 2024-02-05 13:50:58 +00:00
Tapani Pälli
1693d0b857 anv: implement Wa_16014912113 
When URB state for DS changes, we need to emit URB setup for VS with
256 handles and 0 for rest, commit this using a HDC flush before
setting real values.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26920>
 2024-02-05 13:50:58 +00:00
Tapani Pälli
263f693760 iris: implement Wa_16014912113 
When URB state for DS changes, we need to emit URB setup for VS with
256 handles and 0 for rest, commit this using a HDC flush before
setting real values.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26920>
 2024-02-05 13:50:58 +00:00
Tapani Pälli
bdc7d32e93 blorp/crocus: refactor blorp_emit_urb_config 
Patch changes blorp_emit_urb_config to use intel_urb_config so that we
can use it later to communicate blorp urb configuration for drivers.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26920>
 2024-02-05 13:50:58 +00:00
Tapani Pälli
829e4fe877 intel/common: provide a helper for urb setup comparison 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26920>
 2024-02-05 13:50:58 +00:00
Tapani Pälli
a1b885b482 intel: refactor urb configuration, add intel_urb_config 
Patch adds a structure holding urb configuration. This makes it nicer
to pass it around as example for blorp. We need to be able to sometimes
compare with last urb configuration to be able to implement some
workaround.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26920>
 2024-02-05 13:50:58 +00:00
Christian Duerr
49c1b404e5 panfrost: Fix dual-source blending 
If dual blending is enabled, only 1 output is supported. Multiple
outputs confuse the write combining pass in this case, leading to
incorrect output and/or an assert failure in emit_fragment_store.

The fix is straightforward, just skip the speculative emitting of
multiple outputs in the case where dual source blending is enabled.

This also adds an extra sanity check in `pan_nir_lower_zs_store` to
check for only one blend store being present.

Fixes: c65a9be421 ("panfrost: Preprocess shaders at CSO create time")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9487
Co-Authored-By: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26474>
 2024-02-05 13:25:56 +00:00
Sergi Blanch Torne
084f81fd52 Revert "ci: disable Collabora's farm due to maintance" 
This reverts commit 3a2e5c1b77.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27360>
 2024-02-05 12:48:30 +00:00
Job Noorman
29fa1d7f25 ir3: set reconvergence for scan_clusters.macro 
The introduction of block::reconvergence_point happened at the same time
as scan_clusters.macro so we forgot to set it correctly.

Fixes: 60413e11c2 ("ir3: optimize subgroup operations using brcst.active")
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27463>
 2024-02-05 12:28:10 +00:00
Georg Lehmann
cc7400e49c anv: report rotate subgroup feature bits 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27444>
 2024-02-05 11:20:28 +00:00
Georg Lehmann
2ad3b83d23 radv: report rotate subgroup feature bits 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27444>
 2024-02-05 11:20:28 +00:00