We only support equal MB/CTB per slice (with last slice possibly
smaller) and this is not possible to fully describe with libva slice
structure constraints.
Report that we support arbitrary macroblocks per slice, verify if the
slice structure requested by application can be used, otherwise
divide the slices equally to achieve the requested number of slices.
Also stop reporting power of two structure support, as that implies
different size for each slice which cannot be supported.
This fixes issue where slice encoding is not available at all with some
applications (only supporting arbitrary macroblocks) or the number of slices
being different from the requested number.
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30363>
During development of the freedreno's Perfetto producer for a7xx platforms
it was found that the lists of perfcntr countables that were initially
imported were not correct.
The lists are now updated, with the updated countables matching the
countables used in the official profiler tool's counters. While the
Perfetto producer work is still ongoing the fixed lists should already be
useful through fdperf.
Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30406>
A750+ added a special flag that allows HW to correctly interpret UBWC, including
UBWC fast-clear when casting image to a different format permitted by Vulkan.
So it's possible to have UBWC enabled for image that has e.g. R32_UINT and
R8G8B8A8_UNORM in the mutable formats list.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30370>
Our current TLB path would case a job writing to the blit source
to be flushed, causing the TLB store which we would then reload
from memory to do the blit, which is not optimal. With this path,
if the job that writes the blit source has not been flushed, we
will configure it to also do the blit to the destination. This will
avoid the expensive TLB load for the blit and, if glInvalidateFramebuffer
has been used on the blit source, possibly the TLB store as well for
the job writing the blit source.
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30322>
The condition of flat ccs and vram_only checker causes different
aux usage at binding stage. The current design is reusing CCS_E
on Xe2, so we want both Xe2 integrated and discreted GPUs behave
the same way.
Xe2 shouldn't need any special setup of CCS in the loop.
Backport-to: 24.2
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30111>
On pre-Xe2 platforms, the compression on these modifiers that
don't support compression are enabled. The compressed will be
resolved when needed. On Xe2+ we haven't support explicit
resolve, so all the paths to resolves are prohibited now. But
the code is still doing it, causing an assertion failure:
Fixes: vkcube
src/intel/vulkan/anv_private.h:5467:
anv_image_get_fast_clear_type_addr: Assertion
`device->info->ver < 20' failed.
Backport-to: 24.2
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30111>
Unlike on Volta, isetp.x on Maxwell seems to take the accumulator into
account and I don't know exactly how. Fortunately, we can avoid it by
emitting a different 3 instructions. The result is actually a good bit
simpler.
Fixes: efd86d6daa ("nak/builder: Fix isetp64 for pre-Volta")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30402>
The only reason why this hasn't been causing us problems before is
because the only use of ineg in an iadd with a carry-out is ineg64 and
that's basically guaranteed to be folded in NIR because it's unary.
However, if we want to be able to use SrcMod::INeg more, we need to be
more careful about it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30402>
