This allows intel-rt to be turned on in cases where we're on x86_64 and
we're building anv, but otherwise default to off, while still giving
users the power to ignore those defaults if they want to.
Because of the use of `feature.disable_if` this bumps the Meson
requirement to 1.1. I can get rid of that, but it just makes for a lot
more code than using the helper methods
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27645>
Left-shifting by 11*8 or 14*8 is undefined. This fixes many
dEQP-VK.query_pool.statistics_query.* failures (but not pre-existing
flakes) for release builds using clang.
Fixes: 48aabaf225 ("radv: do not harcode the pipeline stats mask for query resolves")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27651>
This seems to be the root cause of the huge performance issue with
GS_FAST_LAUNCH=2 on RDNA3 dGPUs. Probably a firmware bug, but on dGPUs
only, because on RDNA3 APUs this is just working...
With that GS_FAST_LAUNCH=2 can be re-enabled by default on GFX11.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27636>
For non-sparse usage there is no difference between
DRM_XE_VM_BIND_OP_UNMAP_ALL and DRM_XE_VM_BIND_OP_UNMAP but for sparse
the same bo can be bound to more than one virtual address.
Then in a case like:
img = vkCreateImage()
mem = vkAllocateMemory()
vkQueueBindSparse(img, mem)
vkFreeMemory(mem)
Note that the sparse VMA bind still points to the closed bo(done in
vkFreeMemory()), but with DRM_XE_VM_BIND_OP_UNMAP_ALL all VMAs
over the bos are removed.
Access to a unbound VMA has a defined behavior(page fault) while
access to a bound VMA without backing gem/bo don't have defined
behavior.
Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27601>
When running on a detached head (eg. checkout of a tag or a specific
commit), there is no active branch, so we can't perform this check; just
skip it and assume the user knows what they're doing.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27578>
now that zink_gfx_lib_cache::stages_present exists (and is correct),
this value can be used directly to effect cache eviction instead of depending
on the prog->stages_present value, which may not even be the same prog that
owns a given zink_gfx_lib_cache instance
this fixes the case where a shader used in multiple progs with differing shader
masks would never have all its gpl pipelines freed
fixes leaks with caselist:
KHR-Single-GL46.arrays_of_arrays_gl.InteractionUniformBuffers1
KHR-Single-GL46.subgroups.quad.framebuffer.subgroupquadbroadcast_3_float_vertex
Fixes: d786f52f1f ("zink: prevent crash when freeing")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27358>
Offline shader compilation will use json as the source configuration
to accurately instantiate mesa for target hardware. Similar platforms
generate identical shader binaries even though intel_device_info
differs inconsequenially.
Include the shader compilation hash key to device info json files, so
these platforms can be deduplicated.
Closes: #6746
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26844>
This is a more sensible home for intel_dev_info.
Offline shader compilation will take intel_dev_info json files as
input. For that use case, the shader compiler hash value is needed in
the json file.
intel_dev_info will depend on intel/compiler, and must be located in
intel/tools to break a circular meson dependency.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26844>
For anv, use the intel device info hash function instead of
device PCI ID when generating a UUID for the pipeline cache.
PCI ID can vary between on devices which are comparable from the
perspective of the shader compiler. A more precise key eliminates
redundant entries in a multiplatform shader cache.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26844>
For iris, use the intel device info hash function instead of PCI ID in
the renderer name. The renderer is incorporated into the gallium disk
cache for programs, as part of the key for looking up cache entries.
PCI ID can vary between on devices which are comparable from the
perspective of the shader compiler. A more precise key eliminates
redundant entries in a multiplatform shader cache.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26844>
Currently, Intel's shader cache incorporates PCI ID into shader cache
keys.
Many devices with different PCI IDs have identical shader compilation
functionality. Using PCI ID as a component of the shader cache hash
means that a multi-platform shader cache will have redundant,
identical entries for similar platforms.
All Intel compiler functionality is selected based on device
configuration in `struct intel_device_info`. intel_device_info.py
flags all fields accessed by intel/compiler.
This commit generates a hash function incorporating intel/compiler
device info fields. Using this hash function in place of PCI ID will
produce a multiplatform cache with no duplicated content.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26844>
Since GDI doesn't support this format, we need a fallback path to
get contents on-screen if we're not using DXGI. For that scenario,
we allocate a proxy display target and blit during frontbuffer flush.
Once we have that fallback in place, we can override the sw winsys
format support check for that format.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27512>
When the frontend asks for the front buffer, we return an offscreen
surface, when the frontend asks us to flush that surface, we copy it
to the swapchain, and then present remains unchanged.
This means the only reason we need to avoid using a swapchain is if
the app asks for GDI compatibility.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27512>
We already implement all of the relevant bits of this extension, which
is just handling WGL_TYPE_RGBA_FLOAT_ARB for WGL_PIXEL_TYPE_ARB in
wglGetPixelFormatAttrib[i/f]vARB and wglChoosePixelFormatARB. We just
didn't have any float formats enumerated so it was never seen in
practice.
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Jose Fonseca <jose.fonseca@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27512>
It seems like an L3 setting is different between DG2 & MTL, breaking
the L3 coherency with CS.
We can apply the same tile cache flush as we do on TGL for now until
we figure out how to configure L3 properly to avoid this.
Tested with :
$ query_clear_with_blorp_threshold=0 query_copy_with_shader_threshold=0 ./deqp-vk -n dEQP-VK.query_pool.*
to force the shader optimizations.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27597>
