Commit Graph

178079 Commits

Author SHA1 Message Date
Rob Clark
86f5077538 freedreno: Add reformatting commits to .git-blame-ignore-revs
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25337>
2023-09-22 02:07:36 +00:00
Timothy Arceri
dedb2f0208 glsl: remove unused validate_first_and_last_interface_explicit_locations()
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>
2023-09-22 00:41:18 +00:00
Timothy Arceri
7b744bb8df glsl: switch to nir validate_first_and_last_interface_explicit_locations()
Use the new nir version. The glsl ir version will be removed in the
following patch.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>
2023-09-22 00:41:18 +00:00
Timothy Arceri
92f24e6cdc glsl: add nir version of validate_first_and_last_interface_explicit_locations()
The glsl ir version will be removed in a following commit.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>
2023-09-22 00:41:18 +00:00
Timothy Arceri
8bf5c39994 glsl: move get_varying_type() declaration earlier
Required for the following patch to keep this file somewhat organised.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>
2023-09-22 00:41:18 +00:00
Jordan Justen
08735fd90d intel/isl: Build for Xe2
This is only *build* support in isl for Xe2. Before adding LNL PCI
IDs, subsequent patches will fill in ISL updates for Xe2.

Rework:
 * Rohan: Update isl_genX_declare_get_func

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25253>
2023-09-21 18:24:01 +00:00
Jordan Justen
961aa68b23 intel/genxml: Build with gen20.xml
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25253>
2023-09-21 18:24:01 +00:00
Martin Roukala (né Peres)
065ff21bf2 radv/ci: add more tests to the navi10 vkcts flake list
Since I had to aggregate the results of a lot of run, this commit also
ends up ordering some of the flakes to fit the alphabetical order.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25324>
2023-09-21 17:59:05 +00:00
Martin Roukala (né Peres)
8c98ee6f3a radv/ci: move vkcts-navi10 testing to KWS
We now have 2 more navi10 DUTs at KWS, so let's use them to speed
up vkcts testing!

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25324>
2023-09-21 17:59:05 +00:00
Ian Romanick
2157f136d7 nir/rematerialize: Rematerialize ALUs used only by compares with zero
This was 4th on the list of things to try in 3ee2e84c60 ("nir:
Rematerialize compare instructions"). This is implemented as a separate
subpass that tries to find ALU instructions (with restrictions) that are
only used by comparisons with zero that are in turn only used as
conditions for bcsel or if-statements.

There are two restrictions implemented. One of the sources must be a
constant. This is done in an attempt to prevent increasing register
pressure. Additionally, the opcode of the instruction must be one that
has a high probablility of getting a conditional modifier on Intel
GPUs. Not all instructions can have a conditional modifiers (e.g., min
and max), so I don't think there is any benefit to moving these
instructions.

v2: Rebase on many, many recent NIR infrastructure changes.

v3: Make data in commit message more clear. Suggested by Matt. Rebase on
b5d6b7c402 ("nir: Drop most uses if nir_instr_rewrite_src()").

All of the affected shaders on ILK and G45 are in CS:GO. There is some
brief analysis of the changes in the MR.

Reviewed-by: Matt Tuner <mattst88@gmail.com>

Shader-db results:

DG2
total instructions in shared programs: 22824637 -> 22824258 (<.01%)
instructions in affected programs: 365742 -> 365363 (-0.10%)
helped: 190 / HURT: 97

total cycles in shared programs: 832186193 -> 832157290 (<.01%)
cycles in affected programs: 41245259 -> 41216356 (-0.07%)
helped: 208 / HURT: 117

total spills in shared programs: 4072 -> 4060 (-0.29%)
spills in affected programs: 366 -> 354 (-3.28%)
helped: 4 / HURT: 2

total fills in shared programs: 3601 -> 3607 (0.17%)
fills in affected programs: 708 -> 714 (0.85%)
helped: 4 / HURT: 2

LOST:   0
GAINED: 1

Tiger Lake and Ice Lake had similar results. (Ice Lake shown)
total instructions in shared programs: 20320934 -> 20320689 (<.01%)
instructions in affected programs: 236592 -> 236347 (-0.10%)
helped: 176 / HURT: 29

total cycles in shared programs: 849846341 -> 849843856 (<.01%)
cycles in affected programs: 41277336 -> 41274851 (<.01%)
helped: 195 / HURT: 110

LOST:   0
GAINED: 1

Skylake
total instructions in shared programs: 18550811 -> 18550470 (<.01%)
instructions in affected programs: 233908 -> 233567 (-0.15%)
helped: 182 / HURT: 25

total cycles in shared programs: 835910983 -> 835889167 (<.01%)
cycles in affected programs: 38764359 -> 38742543 (-0.06%)
helped: 207/ HURT: 94

total spills in shared programs: 4522 -> 4506 (-0.35%)
spills in affected programs: 324 -> 308 (-4.94%)
helped: 4 / HURT: 0

total fills in shared programs: 5296 -> 5280 (-0.30%)
fills in affected programs: 324 -> 308 (-4.94%)
helped: 4 / HURT: 0

LOST:   0
GAINED: 1

Broadwell
total instructions in shared programs: 18199130 -> 18197920 (<.01%)
instructions in affected programs: 214664 -> 213454 (-0.56%)
helped: 191 / HURT: 0

total cycles in shared programs: 935131908 -> 934870248 (-0.03%)
cycles in affected programs: 75770568 -> 75508908 (-0.35%)
helped: 203 / HURT: 84

total spills in shared programs: 13896 -> 13734 (-1.17%)
spills in affected programs: 162 -> 0
helped: 3 / HURT: 0

total fills in shared programs: 16989 -> 16761 (-1.34%)
fills in affected programs: 228 -> 0
helped: 3 / HURT: 0

Haswell
total instructions in shared programs: 16969502 -> 16969085 (<.01%)
instructions in affected programs: 185498 -> 185081 (-0.22%)
helped: 121 / HURT: 1

total cycles in shared programs: 925290863 -> 924806827 (-0.05%)
cycles in affected programs: 30200863 -> 29716827 (-1.60%)
helped: 100 / HURT: 85

total spills in shared programs: 13565 -> 13533 (-0.24%)
spills in affected programs: 736 -> 704 (-4.35%)
helped: 8 / HURT: 0

total fills in shared programs: 15468 -> 15436 (-0.21%)
fills in affected programs: 740 -> 708 (-4.32%)
helped: 8 / HURT: 0

LOST:   0
GAINED: 1

Ivy Bridge
total instructions in shared programs: 15839127 -> 15838947 (<.01%)
instructions in affected programs: 77776 -> 77596 (-0.23%)
helped: 58 / HURT: 0

total cycles in shared programs: 459852774 -> 459739770 (-0.02%)
cycles in affected programs: 11970210 -> 11857206 (-0.94%)
helped: 79 / HURT: 53

Sandy Bridge
total instructions in shared programs: 14106847 -> 14106831 (<.01%)
instructions in affected programs: 1611 -> 1595 (-0.99%)
helped: 10 / HURT: 0

total cycles in shared programs: 775004024 -> 775007516 (<.01%)
cycles in affected programs: 2530686 -> 2534178 (0.14%)
helped: 55 / HURT: 48

Iron Lake
total cycles in shared programs: 257753356 -> 257754900 (<.01%)
cycles in affected programs: 2977374 -> 2978918 (0.05%)
helped: 12 / HURT: 106

GM45
total cycles in shared programs: 169711382 -> 169712816 (<.01%)
cycles in affected programs: 2402070 -> 2403504 (0.06%)
helped: 12 / HURT: 57

Fossil-db results:

All Intel platforms had similar results. (DG2 shown)
Totals:
Instrs: 193884596 -> 193465896 (-0.22%); split: -0.25%, +0.03%
Cycles: 14050193354 -> 14048194826 (-0.01%); split: -0.34%, +0.33%
Spill count: 114944 -> 100449 (-12.61%); split: -13.59%, +0.98%
Fill count: 201525 -> 179534 (-10.91%); split: -11.22%, +0.31%
Scratch Memory Size: 10028032 -> 8468480 (-15.55%)

Totals from 16912 (2.59% of 653124) affected shaders:
Instrs: 34173709 -> 33755009 (-1.23%); split: -1.41%, +0.19%
Cycles: 2945969110 -> 2943970582 (-0.07%); split: -1.62%, +1.55%
Spill count: 97753 -> 83258 (-14.83%); split: -15.98%, +1.15%
Fill count: 176355 -> 154364 (-12.47%); split: -12.82%, +0.35%
Scratch Memory Size: 8619008 -> 7059456 (-18.09%)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20176>
2023-09-21 16:58:29 +00:00
Pierre-Eric Pelloux-Prayer
60a7c9688c radeonsi: emit framebuffer state after allocating cmask
tex->cmask_base_address_reg and tex->cb_color_info are used in
si_emit_framebuffer_state so we have to re-emit the state when
they're modified.

It's not done in si_alloc_separate_cmask because it cannot
update framebuffer.dirty_cbufs.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9830
Cc: mesa-stable
Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25317>
2023-09-21 16:12:06 +00:00
Emma Anholt
0c1b6af1b6 ci/fastboot: Use a case insensitive match for a fastboot line.
Newer boards like the RB5 have a capital F, so this will make the script
more reusable for drm ci.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25311>
2023-09-21 15:32:30 +00:00
David Rosca
2b1148ca4d radeonsi/vcn: Implement destroy_fence vfunc
Now that fences are correctly cleaned up in frontend, we can store
the fence reference in picture->fence again.

The encoder also needs to implement this vfunc because if a surface
from decoder is used directly as encode input it's now up to encoder
to destroy the fence.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9834

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25296>
2023-09-21 13:30:28 +00:00
David Rosca
24ff1062b1 frontends/va: Destroy fences when destroying surface or context
It is valid to destroy VASurface after destroying VAContext, so we need
to destroy fences of all surfaces that are currently being tracked by a
context when deleting this context.

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25296>
2023-09-21 13:30:28 +00:00
David Rosca
d6b2a624a1 frontends/va: Track surfaces in context
This will be needed to correctly cleanup fences.

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25296>
2023-09-21 13:30:28 +00:00
Roman Stratiienko
8f513813b1 u_gralloc: Add a function that returns gralloc type
This is needed by some drivers to reject the fallback gralloc.

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
2023-09-21 10:50:34 +00:00
Roman Stratiienko
d923d6234d Revert "util: Add NONNULL macro"
We agreed in [1] not to use it since it has little value,
but making a code less readable.

[1]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256

This reverts commit 21dcde096f.

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
2023-09-21 10:50:34 +00:00
Roman Stratiienko
3b6f14c4d3 u_gralloc: Remove usage of NONNULL macro
We agreed in [1] not to use it since it has little value,
but making a code less readable.

[1]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
2023-09-21 10:50:34 +00:00
Roman Stratiienko
28b21fae6e u_gralloc: Remove inline modifiers from the functions
Suggested-by: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
2023-09-21 10:50:34 +00:00
Eric Engestrom
446b0fe8c9 docs: drop outdated and redundant note about the minimum meson version
The documentation we've been keeping up to date is in `docs/meson.rst`.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25322>
2023-09-21 10:41:52 +00:00
Georg Lehmann
336ec2a4b4 aco: simplify masked swizzle dpp selection by removing or_mask first
and_mask and xor_mask alone can represent all patterns without or_mask

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25115>
2023-09-21 10:07:27 +00:00
Eric Engestrom
2009b9b5e2 ci: limit build jobs to 30min so that they can retry when they go wrong
Build jobs should never take more than 1-3 minutes.

These jobs are never slow, either they finish within reasonable time or
something has gone wrong and the job will never terminate, so we should
instead timeout and retry.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24995>
2023-09-21 08:21:04 +00:00
Karol Herbst
33ca3a999c rusticl/kernel: skip adding global id offsets if not used
This allows us to shrink the kernel input buffer quite significantly as
the offset is a vec aligned size_t3 value.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25303>
2023-09-21 07:58:34 +00:00
Karol Herbst
a9f408bd52 rusticl/mesa: fix set_constant_buffer when passing an empty buffer
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25303>
2023-09-21 07:58:34 +00:00
Jordan Justen
f1b9b7f955 intel/fs: Update SSBO & shared uniform block loads for Xe2
Note: lower_lsc_block_logical_send() most likely stills needs some
related updates.

Ref: a358b97c58 ("intel/fs: optimize uniform SSBO & shared loads")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 23:06:16 -07:00
Jordan Justen
9fb2b12c99 intel/compiler: Update RT stack_id access for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 23:06:16 -07:00
Jordan Justen
d371565d34 intel/compiler: Update ray-tracing intrinsic lowering for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 23:06:16 -07:00
Jordan Justen
3d744a6890 intel/compiler: Update lower_trace_ray_logical_send() for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 23:06:16 -07:00
Jordan Justen
9e43fa09a6 intel/compiler: Update emit_rt_lsc_fence() for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 23:06:16 -07:00
Jordan Justen
9846dd798b intel/compiler: Update opt_split_sends() for Xe2 reg size
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 23:06:04 -07:00
Jordan Justen
727ab2c11d intel/compiler/fs: Support Xe2 reg size in assign_curb_setup
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Francisco Jerez
cef4d53daf intel/xe2+: Round up size to reg_unit() in fs_reg_alloc::alloc_spill_reg().
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Francisco Jerez
fe3d90aedf intel/fs/xe2+: Fix calculation of spill message width for Xe2 regs.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Francisco Jerez
791d040104 intel/fs/xe2+: Fix execution width of SHADER_OPCODE_GET_BUFFER_SIZE for SIMD16 EU.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Francisco Jerez
ac4f598577 intel/fs/xe2+: Update regioning lowering offset alignment checks for Xe2 regs.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Francisco Jerez
37e280f28a intel/fs: Lower unsupported regioning with non-trivial 2D regions on FIXED_GRFs.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Caio Oliveira
dd632bf527 intel/fs/xe2+: Update TASK/MESH payload setup for Xe2 reg size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Caio Oliveira
8944ac7d6c intel/fs/xe2+: Update BS payload setup for Xe2 reg size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Francisco Jerez
14e1b9ee69 intel/fs/xe2+: Update TES payload setup for Xe2 reg size.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Francisco Jerez
4b3243104c intel/fs/xe2+: Update TCS payload setup for Xe2 reg size.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Francisco Jerez
6195eac210 intel/fs/xe2+: Update GS payload setup for Xe2 reg size.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Caio Oliveira
28744c8954 intel/compiler/xe2: Account for reg_unit() in TES intrinsics
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Caio Oliveira
9859f5b4d2 intel/compiler/xe2: Account for reg_unit() in TCS intrinsics
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Francisco Jerez
610daa3166 intel/fs/xe2+: Fix payload layout of sampler messages for Xe2 reg size
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Ian Romanick
c9f2857546 intel/compiler/xe2: TXD is lowered to SIMD16 in SIMD32 mode
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Ian Romanick
ef817650c9 intel/compiler/xe2: Use SIMD16 for nir_intrinsic_image_size
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Ian Romanick
0b23df3951 intel/compiler/xe2: Update fs_visitor::setup_vs_payload to account for Xe2 reg size
[ Francisco Jerez: Simplify. ]

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Rohan Garg
42b90f05f6 intel/compiler: Adjust barrier emission for Xe2+
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Francisco Jerez
8b1dc77521 intel/fs/xe2+: Scale BRW_MAX_MSG_LENGTH by native register size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00
Rohan Garg
4de065f6a2 intel/compiler: Adjust fence message lengths for new register width on Xe2+
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
2023-09-20 17:19:36 -07:00