4 Commits

Author	SHA1	Message	Date
Ian Romanick	684ec33c79	intel/compiler: Make the CMPN builder work like the CMP builder ... Since the CMPN builder was never used, there was no reason to make its interface usable. :) Fixes: 2f2c00c727 ("i965: Lower min/max after optimization on Gen4/5.") Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9027>	2021-02-17 19:52:24 +00:00
Ian Romanick	d0ce24c8ca	intel/vec4: Remove inline lowering of LRP ... Since dd7135d55d ("intel/compiler: Use the flrp lowering pass for all stages on Gen4 and Gen5"), it's not possible to get to this function on GPUs that don't have a LRP instruction. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6826>	2020-09-28 11:43:10 -07:00
Matt Turner	89fe5190a2	intel/compiler: Lower flrp32 on Gen11+ ... The LRP instruction is no more. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>	2018-02-28 11:15:47 -08:00
Jason Ekstrand	700bebb958	i965: Move the back-end compiler to src/intel/compiler ... Mostly a dummy git mv with a couple of noticable parts: - With the earlier header cleanups, nothing in src/intel depends files from src/mesa/drivers/dri/i965/ - Both Autoconf and Android builds are addressed. Thanks to Mauro and Tapani for the fixups in the latter - brw_util.[ch] is not really compiler specific, so it's moved to i965. v2: - move brw_eu_defines.h instead of brw_defines.h - remove no-longer applicable includes - add missing vulkan/ prefix in the Android build (thanks Tapani) v3: - don't list brw_defines.h in src/intel/Makefile.sources (Jason) - rebase on top of the oa patches [Emil Velikov: commit message, various small fixes througout] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>	2017-03-13 11:16:34 +00:00