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Eric Engestrom
fd35e59139 ci: avoid running hardware jobs if lint fails - now on LAVA too! 
I missed this in !23774.

Fixes: a1c1cce9df ("ci: avoid running hardware jobs if there are already trivial issues")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24121>
 2023-07-12 19:31:01 +00:00
Alyssa Rosenzweig
ef80f81c8f zink: Switch to register intrinsics 
SPIR-V does not have anything like nir_register natively, so we were already
inserting loads/stores for register sources/destinations. That means it's easy
to switch to register intrinsics, getting explicit load_reg/store_reg intrinsics
in the NIR and translating those to the SPIR-V load/stores, dropping the
handling for nir_register. There's no need to use any of the chasing helpers for
coalescing the load/stores, like a hardware backend would. (In
fact, the underlying Vulkan driver will probably turn this back into SSA.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24111>
 2023-07-12 19:05:09 +00:00
Dylan Baker
fac4f526ac VERSION: bump to 23.3.0-devel 
For further development

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24124>
 2023-07-12 11:13:17 -07:00
Karol Herbst
2c48ce81a8 api/icd: drop static lifetime from get_ref return type 
This was never correct as the object pointed to can be destroyed at any
moment.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24061>
 2023-07-12 15:18:22 +00:00
Karol Herbst
d653eb8a9a rusticl/device: make it &'static 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24061>
 2023-07-12 15:18:22 +00:00
Karol Herbst
afe95b613c rusticl: Replace &Arc<Device> with &Device 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24061>
 2023-07-12 15:18:22 +00:00
Karol Herbst
5bd235189a rusticl/kernel: silence newer clippy warning 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24061>
 2023-07-12 15:18:22 +00:00
Eric Engestrom
a1c1cce9df ci: avoid running hardware jobs if there are already trivial issues 
Suggested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23774>
 2023-07-12 14:08:42 +00:00
Danylo Piliaiev
feaa12c7c6 freedreno/regs: Document a7xx CP_BV_BR_COUNT_OPS 
Fully tested on HW. Credits to Connor Abbott for finding out how
it works.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:28 +00:00
Danylo Piliaiev
271ba74766 freedreno/regs: Properly document a7xx CP_EVENT_WRITE, CP_WAIT_TIMESTAMP 
Event write is changes so much in a7xx that it makes sense to
create a new event CP_EVENT_WRITE7.

All credits to Connor Abbott for finding out what different flags
in these commands are doing.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:28 +00:00
Danylo Piliaiev
aceb82b80e tu: Use reg usage tables for stale reg dbg option 
Defining regs to stomp as ranges in a separate header is a mistake
from maintenance standpoint. Now we have this information at the
point where reg is defined.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:28 +00:00
Danylo Piliaiev
aecb732320 tu: Allow reg stomping of compute related registers 
We don't use draw states for dispatches, so the bound pipeline
could be overwritten by reg stomping in a renderpass or blit.

The solution is to re-emit pipeline's IB on every dispatch if
reg stomping is used.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:28 +00:00
Danylo Piliaiev
dac8d371e1 freedreno/regs: Define usage for all a6xx/a7xx regs 
Could be used for knowing which regs to stomp and to verify that
only appropriate regs are emitted.

Each register that is actually being used by driver should have "usage"
defined, currently there are following usages:
- "cmd" - the register is used outside of renderpass and blits,
		roughly corresponds to registers used in ib1 for Freedreno
- "rp_blit" - the register is used inside renderpass or blits
		(ib2 for Freedreno)

It is expected that register with "cmd" usage may be written into only at
the start of the command buffer (ib1), while "rp_blit" usage indicates that
register is either overwritten by renderpass/blit (ib2) or not used if not
overwritten by a particular renderpass/blit.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:28 +00:00
Danylo Piliaiev
c62b0cd4f8 freedreno/regs: Generate per-gen reg usage tables 
"reg" and "array" now could have `usage="a,b,c"` attribute, for each
usage a separate array is generated.

Would be used for register stomping debug option.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:28 +00:00
Danylo Piliaiev
463db34258 freedreno/regs: Fix a7xx SP_FS_PREFETCH definition 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:28 +00:00
Danylo Piliaiev
6f3117fbce freedreno/regs: Add more a7xx regs and reg fields 
Deduced from a740 cmdtraces from running CTS on prop driver.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:28 +00:00
Danylo Piliaiev
95354ab679 freedreno/regs: Add some new a7xx events 
There are many more a7xx events but they are left for later.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:28 +00:00
Danylo Piliaiev
5928ac6b64 freedreno/regs: Add 2 new a7xx modes to CP_COND_REG_EXEC 
Also reworked how CP_COND_REG_EXEC is defined to print
less irrelevant fields.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:28 +00:00
Danylo Piliaiev
27312eb386 freedreno/regs: a7xx has a new source type CP_REG_TEST 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:28 +00:00
Danylo Piliaiev
853d64ae55 freedreno/regs: Add a7xx pseudo-regs to CP_SET_PSEUDO_REG 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:28 +00:00
Danylo Piliaiev
1dc044764d freedreno/regs: Clarify polling on a7xx for CP_WAIT_REG_MEM/CP_COND_WRITE5 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:28 +00:00
Danylo Piliaiev
1f192e49b6 freedreno/regs: Document a7xx CP_MODIFY_TIMESTAMP 
Clears, adds to local, or adds to global timestamp

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:27 +00:00
Danylo Piliaiev
ed6394fda7 freedreno/regs: Document CP_MEM_TO_SCRATCH_MEM 
Best guess is that it is a faster way to fetch all the VSC_STATE registers
and keep them in a local scratch memory instead of fetching every time
when skipping IBs.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:27 +00:00
Connor Abbott
912bafbdd5 freedreno/regs: Document a7xx CP_FIXED_STRIDE_DRAW_TABLE 
Executes an array of fixed-size command buffers where each
buffer is assumed to have one draw call, skipping buffers with
non-visible draw calls.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:27 +00:00
Danylo Piliaiev
8185fac66b freedreno/regs: More CP commands are the same on a7xx as on a6xx 
These ones are seen to be used by blob in CTS, the rest a6xx commands
were not seen beeing used.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:27 +00:00
Danylo Piliaiev
11cc456117 freedreno/regs: Change a7xx regs to have open range for generation 
Until proven otherwise regs stay the same between gens.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:27 +00:00
Danylo Piliaiev
3ba1d230ad freedreno/rnn: Take into account array's variant for regs 
Otherwise even if array only exists in one generation the code for
its registers is generated for all gens.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:27 +00:00
Danylo Piliaiev
dfe650f3f9 freedreno/rnn: Make addvariant work for fields in the same reg 
Previously if addvariant was processed after other fields in the reg
these fields would never get matched. Fix this by moving bitfields that
add variant to the beginning of the list.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:27 +00:00
Danylo Piliaiev
15db60fbbc freedreno/rnn: Fix addvariant being set effectively once 
Each time addvariant was added it was added to the end of ctx->vars
list, without previous variant being removed. While the check for
variant tests only the first one that has expected enum name.

Fix this by updating `variant` instead of appending new one if variant
with such enum already exists.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:27 +00:00
Danylo Piliaiev
148f214dae freedreno/regs: Print xml validation error if validation fails 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23881>
 2023-07-12 13:33:27 +00:00
Eric Engestrom
431bbea840 meson: clarify what "off-screen rendering" means 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24114>
 2023-07-12 12:38:14 +00:00
Eric Engestrom
4ef16e34a8 meson: clarify description of opengl option 
There was some confusion from users as to whether disabling this option
disables OpenGL ES as well, so let's remove the confusing "all versions"
note and specify this affects "desktop OpenGL" only.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24113>
 2023-07-12 12:24:43 +00:00
Marcin Ślusarz
a762fa27db anv: limit stack usage for anv_surface_state 
Each one is 136 bytes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24109>
 2023-07-12 12:00:10 +00:00
Marcin Ślusarz
deaf4f2d57 anv: pass anv_surface_state using a pointer 
It's 136 bytes, so passing it by stack is wasteful.

CID: 1531860

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24109>
 2023-07-12 12:00:09 +00:00
Marcin Ślusarz
fb070b1dfd anv: fix how NULL buffer_view is handled in anv_descriptor_set_write_buffer_view 
CID: 1531855

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24109>
 2023-07-12 12:00:09 +00:00
Timur Kristóf
127999989a aco: Add MESA_SHADER_KERNEL to instruction selection setup. 
Treat it the same way as MESA_SHADER_COMPUTE.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24112>
 2023-07-12 11:24:44 +00:00
Eric Engestrom
6934efc15d broadcom/ci: add the renderonly folder to things that can affect v3d & vc4 
Also, move the v3d/vc4 lines together so it's clearer.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24105>
 2023-07-12 10:51:31 +00:00
Christian Gmeiner
f831883af6 nir/lower_tex: optimize offset lowering for has_texture_scaling 
Generates much better code and even helps to beat a blob driver.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24054>
 2023-07-12 10:03:06 +00:00
Christian Gmeiner
9383009809 nir: rename has_txs to has_texture_scaling 
Convert it to an opt-in for backends to prefer and use nir_load_texture_scale
instead of txs for nir lowerings.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Suggested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24054>
 2023-07-12 10:03:06 +00:00
Christian Gmeiner
9ddedf4554 nir: rename intrinsic to have a more generic nameing 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24054>
 2023-07-12 10:03:06 +00:00
Eric Engestrom
dd81c03ab1 etnaviv/ci: drop duplicate line in etnaviv files list 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24106>
 2023-07-12 09:29:56 +00:00
Karol Herbst
2c3b624300 nvc0: backport fp helper invocation fix to 2nd gen Maxwell+ 
Ben prefers that we use the firmware method where possible.

Cc: mesa-stable
Signed-off-by: Karol Herbst <git@karolherbst.de>
Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23802>
 2023-07-12 08:45:13 +00:00
Hyunjun Ko
0c778ec3c8 anv: Adds a workaround for HEVC decoding on some old platforms. 
HEVC support on Gfx9 is only available on VCS0. So limit the number of video queues
to the first VCS engine instance.

We should be able to query HEVC support from the kernel using the engine query uAPI,
but this appears to be broken : https://gitlab.freedesktop.org/drm/intel/-/issues/8832

When this bug is fixed we should be able to check HEVC support to determine the
correct number of queues.

Closes: mesa/mesa#9172, mesa/mesa#9314

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24065>
 2023-07-12 15:34:28 +09:00
Dave Airlie
ad980dc699 ci: update fails for fixed tests due to llvmpipe linear changes. 
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24066>
 2023-07-12 02:17:26 +00:00
Dave Airlie
a07fa6516b llvmpipe/linear: add support for rgba color buffers. 
This adds support to the linear rast for rgba outputs.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24066>
 2023-07-12 02:17:26 +00:00
Dave Airlie
f96b6027a1 llvmpipe/linear: add support for sampling when cbuf order is different. 
This rewrites bgra sampling when the output is rgba,
and vice-versa.

It allows to skip swaps if the sampling and cbuf match.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24066>
 2023-07-12 02:17:26 +00:00
Dave Airlie
a3f586685d llvmpipe/linear: add sample routines for swapping r/b channels 
This lets rgba textures be sampled in linear mode.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24066>
 2023-07-12 02:17:26 +00:00
Dave Airlie
70f49c78cc llvmpipe/linear/tgsi: calculate num_texs properly for nir. 
This is a bit hacky, but it does the right thing and counts the number
of textures instructions so the linear path can work for multiple textures.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24066>
 2023-07-12 02:17:26 +00:00
Dave Airlie
e43804ba65 llvmpipe/linear: refactor linear samplers into templated code. 
Before adding new copies of all of these for swapping start by
refactoring into macro templated code.

I avoided using inline functions because I want to test with
opts turned down, and this will kill perf.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24066>
 2023-07-12 02:17:26 +00:00
Faith Ekstrand
0230179f8b freedreno/ci: Update pixmark piano checksums 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
 2023-07-12 01:34:27 +00:00