Commit Graph

47 Commits

Author SHA1 Message Date
Dave Airlie
be5276ae7d gallium: add support for LODQ opcodes.
This opcode provide support for GL_ARB_texture_query_lod,

Signed-off-by: Dave Airlie <airlied@redhat.com>
[imirkin: rebase, docs update]
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-04-07 01:06:18 -04:00
Dave Airlie
76ba50a25a mesa/soft/llvmpipe: add fake MSAA support
This adds a gallium cap that allows us to fake GL3.0 by
not exposing MSAA on sw rendering.
It also forces the extra extensions needed for GL3.2.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-04-02 12:12:04 +10:00
Chia-I Wu
5ecdd7ba22 ilo: add support for PIPE_QUERY_PIPELINE_STATISTICS 2014-03-10 16:43:53 +08:00
Chia-I Wu
345bf92f13 ilo: print a warning when PPGTT is disabled
Despite what the PRMs say, the driver appears to work fine when PPGTT is
disabled.  But at least print a warning in that case.
2014-03-10 16:42:42 +08:00
Chia-I Wu
747627d045 ilo: require hardware logical context support
The code paths are not tested for a while, and have some known issues.
2014-03-10 16:42:42 +08:00
Chia-I Wu
0b462d3ab1 ilo: move ring types to winsys
It results in less code despite that i915_drm.h specifies the ring type as
part of the execution flags.
2014-03-10 16:42:42 +08:00
Chia-I Wu
42c1ce4c03 ilo: winsys may limit the batch buffer size
The maximum batch buffer size is determined at the time of
drm_intel_bufmgr_gem_init().  Make sure the pipe driver does not exceed the
limit.
2014-03-10 16:42:42 +08:00
Chia-I Wu
a434ac045e ilo: PIPE_CAP_QUERY_TIMESTAMP may not be supported
Reading TIMESTAMP register may fail, depending on both kernel and hardware.
2014-03-10 16:42:42 +08:00
Chia-I Wu
f2aabecbb0 ilo: remove intel_winsys_enable_reuse()
It should be an (winsys) implementation detail.
2014-03-10 16:42:41 +08:00
Marek Olšák
db8886ed09 gallium: the other drivers don't support ARB_buffer_storage
Reviewed-by: Fredrik Höglund <fredrik@kde.org>
2014-02-25 16:07:33 +01:00
Dave Airlie
2fcbec48d7 gallium: add texture gather support to gallium (v3)
This adds support to gallium for a TG4 instruction,
and two CAPs. The first CAP is required for GL_ARB_texture_gather.

The second CAP is required to expose GL_ARB_gpu_shader5.

However so far we haven't found any hardware that natively
exposes the textureGatherOffsets feature from GL, so just
lower it for now. If hardware appears for this we can add
another CAP to allow TG4 to take 4 offsets.

v2: add component selection src and a cap to say
hw can do it. (st can use to help control
GL_ARB_gpu_shader5/GLSL 4.00). Add docs.

v3: rename to SM5, add docs.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-02-25 13:29:17 +10:00
Grigori Goronzy
d34d5fddf8 gallium: add geometry shader output limits
v2: adjust limits for radeonsi and llvmpipe
v3: add documentation

Cc: "10.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2014-02-09 23:31:38 +01:00
Marek Olšák
0354b769c2 gallium: remove PIPE_CAP_MAX_COMBINED_SAMPLERS
This can be derived from the shader caps.

All GPUs from ATI/AMD, NVIDIA, and INTEL have separate texture slots
for each shader stage.
2014-02-04 20:19:16 +01:00
Siavash Eliasi
205e624048 ilo: Set PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT to 64
Ian manually ran the map_buffer_range* tests and the
arb_map_buffer_alignment-* tests, but he did not do a full piglit run.

v2 (idr): Use 64 instead of 4096

Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2014-01-29 09:11:39 -07:00
Marek Olšák
d382e90614 gallium: remove PIPE_CAP_SCALED_RESOLVE
If any driver doesn't support this, it can use a blit after resolving
the samples.

Reviewed-by: Brian Paul <brianp@vmware.com>
2014-01-23 01:47:14 +01:00
Chia-I Wu
76edf44f9e ilo: enable HiZ
The support is still early.  Fast depth buffer clear is not enabled yet.

HiZ can be forced off with ILO_DEBUG=nohiz.
2014-01-08 18:11:36 +08:00
Marek Olšák
1a02bb71dd gallium: add support for AMD_vertex_shader_layer 2013-12-03 19:39:13 +01:00
Roland Scheidegger
2983c039df gallium: new shader cap bit for the amount of sampler views
Ever since introducing separate sampler and sampler view max this was really
missing.
Every driver but llvmpipe reports the same number as number of samplers for
now, so nothing should break.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-11-28 04:02:18 +01:00
Chia-I Wu
d2fdc0d634 ilo: minor cleanups for recent interface changes
Kill ilo_bind_sampler_states2 and ilo_set_sampler_views2.  Map
PIPE_FORMAT_R10G10B10A2_UINT to BRW_SURFACEFORMAT_R10G10B10A2_UINT.
2013-10-28 11:40:41 +08:00
Ilia Mirkin
12d39b4fa8 gallium: add PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
This CAP will determine whether ARB_framebuffer_object can be enabled.
The nv30 driver does not allow mixing swizzled and linear zsbuf/cbuf
textures.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2013-10-26 01:36:07 +02:00
Chia-I Wu
ce87c51e9a ilo: add ILO_DEBUG=flush
When specified, ilo will print a line similar to

  cp flushed for render with 949+888 DWords (22.4%) because of frame end

for every ilo_cp_flush() call.
2013-08-20 13:54:39 +08:00
Chia-I Wu
216a576e11 ilo: add ILO_DEBUG=draw
It can print out pipe_draw_info and the dirty bits set, useful for debugging.
2013-08-20 13:54:38 +08:00
Christian König
a15cbabb8b vl: add entrypoint to get_video_param
Signed-off-by: Christian König <christian.koenig@amd.com>
2013-08-19 10:21:15 +02:00
Rico Schüller
d1ba1055d9 vl: Add support for max level query v2
This patch adds the level query support to the video decoders
and uses some more reasonable defaults.

v2: (ck) add commit message

Reviewed-by: Christian König <christian.koenig@amd.com>
2013-08-14 13:20:01 +02:00
Tom Stellard
4e90bc9a12 gallium: Add PIPE_CAP_ENDIANNESS
Cc: mesa-stable@lists.freedesktop.org
[ Francisco Jerez: Fix "PIPE_ENDIAN_SMALL" in the documentation,
  define PIPE_ENDIAN_NATIVE. ]
2013-07-22 22:43:17 +02:00
Chia-I Wu
79bc245c01 ilo: reduce PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS to 12
So that there are at most (2^22 * 6) texels, lower than the 2^26 limit.
2013-07-11 08:03:27 +08:00
Marek Olšák
30c3e8718d mesa,glsl,gallium: remove GLSLSkipStrictMaxVaryingLimitCheck and dependencies
Not needed with do_dead_builtin_varyings.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-07-02 17:02:14 +02:00
Chia-I Wu
95c21f12f3 ilo: support PIPE_CAP_USER_INDEX_BUFFERS
We want to access the user buffer, if available, when primitive restart is
enabled and the restart index/primitive type is not natively supported.

And since we are handling index buffer uploads in the driver with this change,
we can also work around misalignment of index buffer offsets.
2013-06-26 16:42:46 +08:00
Chia-I Wu
3eb6754e94 ilo: support PIPE_CAP_USER_CONSTANT_BUFFERS
We need it for HUD support, and will need it for push constants in the future.
2013-06-26 16:42:45 +08:00
Chia-I Wu
5f15050dc9 ilo: bump up PIPE_CAP_GLSL_FEATURE_LEVEL to 140
With UBO and TBO support, we are supposedly good to claim GLSL 1.40.
2013-06-13 23:47:18 +08:00
Chia-I Wu
cdfb2163c4 ilo: get rid of function tables in winsys
We are moving toward making struct intel_bo alias drm_intel_bo.  As a first
step, we cannot have function tables.
2013-06-12 17:46:52 +08:00
Chia-I Wu
9b34a7f29a ilo: advertise PIPE_CAP_CUBE_MAP_ARRAY
It was supported but not advertised.  Also remove TODO tag for
PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT, as it is not a TODO.
2013-06-07 15:37:40 +08:00
Chia-I Wu
27804b2fc7 ilo: enable bo reuse
This magical line of code must have got lost at some point in the history...
2013-06-07 11:28:20 +08:00
Chia-I Wu
70e78211d6 ilo: introduce vertex element CSO
Introduce ilo_ve_cso and initialize it in create_vertex_elements_state().
This commit goes a step further by setting up mappings from HW VB to PIPE VB,
which we failed to do previously.  That allows us to support instanced
rendering.
2013-06-07 11:13:15 +08:00
Chia-I Wu
130364ad1d ilo: switch to ilo states for CLIP and SF stages
Define and use

 struct ilo_viewport_state;
 struct ilo_scissor_state;

in ilo_context.
2013-06-07 11:13:14 +08:00
Chia-I Wu
3a5dd39b1d ilo: add support for indirect access of CONST in FS
Unlike other register files, CONST is read with a message and indirect access
is easier to implement.
2013-05-27 12:30:51 +08:00
Chia-I Wu
fb40aca879 ilo: add support for texture buffer objects
Take care of sampler views that have buffers as the underlying resources.
Update caps related to TBOs.
2013-05-27 11:02:57 +08:00
Chia-I Wu
bd8090a5af ilo: update headers from i965
Mainly for MI_LOAD_REGISTER_IMM and BCS_SWCTRL.
2013-05-21 11:47:19 +08:00
Chia-I Wu
6b894e6900 ilo: add support for stencil resources on GEN7+
For allocations, we need to support stencil-only and separate stencil
resources.  For mapping, we need to support software tiling and
packing/unpacking for separate stencil resources.
2013-05-16 18:20:17 +08:00
Courtney Goeltzenleuchter
daa90f91ff ilo: Add support for HW primitive restart.
Now tells Gallium that ilo supports primitive restart.
Updated ilo_draw_vbo to be able to check that the indexed
primitive being rendered can actually be supported in HW. If not,
will break up into individual prims similar to what Mesa does.

[olv: a minor fix after rebasing and formatting]
2013-05-10 00:06:14 +08:00
Chia-I Wu
22c5e048bd ilo: fix PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
On GEN7+, is->dev.has_gen7_sol_reset is required.
2013-05-01 17:41:39 +08:00
Chia-I Wu
16f81fcf1e ilo: enable SO support on GEN7 2013-05-01 17:36:44 +08:00
Chia-I Wu
ce188bb252 ilo: move device limits to ilo_dev_info or to GPEs
It seems a bit weird to have device limits in a context.
2013-05-01 11:23:11 +08:00
Chia-I Wu
bb1f635dcc ilo: add ilo_dev_info shared by the screen and contexts
The struct is used to describe the device information, such as PCI ID, GEN,
GT, and etc.
2013-05-01 11:20:41 +08:00
Chia-I Wu
babb2b5c50 ilo: hook up pipe_screen param and fence functions 2013-04-26 16:16:42 +08:00
Chia-I Wu
e74d67738d ilo: add debug flags settable through ILO_DEBUG 2013-04-26 16:16:42 +08:00
Chia-I Wu
63b5720105 ilo: new pipe driver for Intel GEN6+
This commit adds some boilerplate code.  The header files found under include/
are copied from i965.
2013-04-26 16:16:41 +08:00