Commit Graph

48 Commits

Author SHA1 Message Date
Eric Anholt
827ba44f6e intel: Remove non-GEM support.
This really isn't supported at this point.  GEM's been in the kernel for
a year, and the fake bufmgr never really worked.
2009-11-19 11:47:22 +01:00
Eric Anholt
bb2dd50be0 intel: Remove obsolete comment about GEM in the spans code. 2009-11-06 11:37:31 -08:00
Brian Paul
bcbfda71b0 intel: avoid unnecessary front buffer flushing/updating
Before, if we just called glXMakeCurrent() and didn't render anything we'd
still trigger a flushFrontBuffer() call.

Now only set the intel->front_buffer_dirty field at state validation time
just before we draw something.

NOTE: additional calls to intel_check_front_buffer_rendering() might be
needed if I missed some rendering paths.
2009-11-03 09:52:25 -07:00
Eric Anholt
7c8bed62e0 intel: Use GTT mapping when available for swrast.
This improves piglit quick.tests runtime from 19:33 minutes to 6:06 on
my GM45.  It should also hide most of the A17 swizzling issues, though
they'll still exist when swapping occurs (which is the kernel's problem
either way).
2009-10-30 17:35:12 -07:00
Eric Anholt
21a3a79371 intel: Fix up z24_x8 depth spans since the texformat merge. 2009-10-30 17:35:11 -07:00
Brian Paul
409469fb70 intel: fix up some XRGB breakage
We weren't choosing the right XRGB span functions for reading the
framebuffer.  XRGB formats still aren't turned on yet though.
2009-10-30 09:13:04 -06:00
Brian Paul
4a253431ab intel: update intel_create_renderbuffer(format), add XRGB support
Pass a gl_format to intel_create_renderbuffer() instead of GLenum.
Add cases for MESA_FORMAT_XRGB8888 textures and renderbuffers.
However, we don't yet create any renderbuffers or textures with that
format.  It seems the default alpha value is zero instead of one.
Need to investigate that first.
2009-10-29 19:12:50 -06:00
Brian Paul
1f196b786d Merge branch 'texformat-rework'
Conflicts:
	src/mesa/drivers/dri/radeon/radeon_fbo.c
	src/mesa/drivers/dri/s3v/s3v_tex.c
	src/mesa/drivers/dri/s3v/s3v_xmesa.c
	src/mesa/drivers/dri/trident/trident_context.c
	src/mesa/main/debug.c
	src/mesa/main/mipmap.c
	src/mesa/main/texformat.c
	src/mesa/main/texgetimage.c
2009-10-28 21:24:11 -06:00
Brian Paul
7d56caabe4 Merge branch 'mesa_7_6_branch'
Conflicts:

	src/mesa/shader/lex.yy.c
	src/mesa/shader/program_lexer.l
2009-10-28 11:33:51 -06:00
Brian Paul
b7eea8c616 intel: added region draw_x/y offsets in x/y_tile_swizzle() funcs
This fixes the second part of bug 23552.
2009-10-27 17:35:30 -06:00
Brian Paul
68d94a608a intel: use MESA_FORMAT_S8_Z24 format and avoid z24s8/s8z24 conversions 2009-10-21 20:02:33 -06:00
Brian Paul
45e76d2665 mesa: remove a bunch of gl_renderbuffer fields
_ActualFormat is replaced by Format (MESA_FORMAT_x).
ColorEncoding, ComponentType, RedBits, GreenBits, BlueBits, etc. are
all replaced by MESA_FORMAT_x queries.
2009-10-08 20:27:27 -06:00
Brian Paul
3e34a2a2b9 drivers: don't include texformat.h
And remove other unneeded #includes while we're at it.
2009-10-05 18:11:37 -06:00
Eric Anholt
7d4b7460b0 i915: Enable ARB_vertex_shader for both i915 and i830.
Since the TNL is all done in software anyway, it should be the same to
the user who's probably using ARB_vertex_program otherwise, but gives them
a nicer programming environment.
2009-10-01 14:31:03 -07:00
Brian Paul
1f7c914ad0 mesa: replace gl_texture_format with gl_format
Now gl_texture_image::TexFormat is a simple MESA_FORMAT_x enum.
ctx->Driver.ChooseTexture format also returns a MESA_FORMAT_x.
gl_texture_format will go away next.
2009-09-30 20:28:45 -06:00
Brian Paul
aa522e6cc4 intel: minor code clean-ups 2009-09-14 12:42:18 -06:00
Brian Paul
8ec456c68c intel: fix renderbuffer map/unmap regression
Commit 36dd53a3cd caused a few regressions
because the glReadBuffer() buffer wasn't getting mapped when GL_READ_BUFFER
!= GL_DRAW_BUFFER.
2009-09-14 12:42:18 -06:00
Eric Anholt
36dd53a3cd intel: Don't forget to map the depth read buffer in spans.
This broke BlitFramebufferEXT(GL_DEPTH_BUFFER_BIT).
2009-09-10 11:16:18 -07:00
Brian Paul
4d24feddff intel: fix typo: s/softare/software/ 2009-08-07 09:50:37 -06:00
Eric Anholt
2c30fd84df intel: Add support for argb1555, argb4444 FBOs and fix rgb565 fbo readpixels.
Also enable them all regardless of screen bpp, as 32 bpp what I've been
testing against, and haven't been able to detect any screen bpp-specific
troubles with them.
2009-04-16 12:04:30 -07:00
Eric Anholt
2b34275a78 intel: Add span code for z24 without stencil.
It seems that in this case the Mesa code is handing us x8z24 values instead
of z24s8 values, so we need to not do the rotation.  Fixes half of OGLconform
depthrange.c.

Bug #19447.
2009-02-26 00:13:26 -08:00
Eric Anholt
43a4543946 intel: make template wrappers for the spans templates.
This is insanity, but so is copying the same blocks containing the actual
interesting code in the file three times each for the different tile formats.
2009-02-25 23:57:00 -08:00
Brian Paul
ba3aadf354 intel: fix check for Y orientation in span functions. 2009-01-29 14:57:16 -07:00
Eric Anholt
65d39a9eed intel: clean up more pf mess. 2009-01-27 12:05:47 -08:00
Ian Romanick
03188b09e0 intel: SW fallback maps texture images, not texture coordinates 2009-01-14 12:48:22 -08:00
Eric Anholt
0cade4de4f intel: Don't keep intel->pClipRects, and instead just calculate it when needed.
This avoids issues with dereferencing stale cliprects around intel_draw_buffer
time.  Additionally, take advantage of cliprects staying constant for FBOs and
DRI2, and emit cliprects in the batchbuffer instead of having to flush batch
each time they change.
2008-10-28 13:23:33 -07:00
Brian Paul
ecadb51bbc mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template 2008-09-18 15:17:05 -06:00
Eric Anholt
35fd72756a intel: track move of bo_exec from drivers to bufmgr. 2008-09-10 13:59:45 -07:00
Dave Airlie
f75843a517 Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c.
2008-08-24 17:59:10 +10:00
Dave Airlie
7c81124d7c Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05.

Conflicts:

	src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-08-24 17:52:40 +10:00
Eric Anholt
53675e5c05 Merge branch 'drm-gem'
Conflicts:

	src/mesa/drivers/dri/intel/intel_span.c
	src/mesa/main/fbobject.c

This converts the i915 driver to use the GEM interfaces for object management.
2008-08-08 15:32:24 -07:00
Xiang, Haihao
8e8019b49a dri: Fix write/read depth buffer issue under 16bpp mode. See bug #16646 2008-08-05 11:34:26 +08:00
Eric Anholt
902e401a38 intel: Don't return a renderbuffer with alpha when just GL_RGB is requested.
Fixes oglconform rbGetterFuncs testcase.  The span code for this mode hasn't
actually been tested.
2008-07-26 17:39:23 -07:00
Eric Anholt
2e37143800 intel: Add a little span cache to spead up readpixels by cutting syscalls. 2008-07-23 10:21:25 -07:00
Eric Anholt
d2d5abfaeb intel-gem: Use pread/pwrite for span access.
This will avoid clflushing entire buffers for small acesses, such as those
commonly used by regression tests.
2008-07-23 10:21:25 -07:00
Eric Anholt
bdaa06ad63 intel: move renderbuffer mapping to separate functions.
This lets us avoid duplicated code for doing so, including the depthstencil
paths that aren't covered by SpanRenderStart/Finish.  Those paths were
missing the span funcs setup, leading to a null dereference in the fbotexture
demo.
2008-07-23 10:21:24 -07:00
Eric Anholt
a5f02368d2 intel-gem: Disable spantmp sse/mmx functions when tile swizzling.
Those functions rely on being able to treat the GET_PTR returned value as an
array indexed by x, but that's not the case for our tiling.

Bug #16387
2008-07-15 13:21:37 -07:00
Eric Anholt
2e841880cf drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes. 2008-07-11 18:58:19 -07:00
Eric Anholt
def6e4f420 intel: span rendering requires just a flush before starting, not finish.
The dri_bo_map()s that follow will take care of idling the hardware as needed.
2008-07-02 11:49:10 -07:00
Eric Anholt
4b3ed4d2d1 intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.
Apparently in Y mode we get bit 6 ^ bit 9.  The reflect demo in 'd' mode now
displays correctly.
2008-07-02 10:21:44 -07:00
Eric Anholt
19f585a3cf intel-gem: Fix Y-tiling span setup.
The boolean that the server gives us for whether the region is tiled was
getting used as the enum for what tiling mode.  Instead, guess the correct
tiling in screen setup.

Also, fix the Y-tiling pitch setup.  The pitch to the next tile in Y is
32 scanlines, not 8.
2008-07-02 09:10:21 -07:00
Eric Anholt
e74f54793e intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode.
It turns out that it's not just deviceID dependent, and there's some additional
undefined factor that determines the bit 6 swizzling.  It's now controllable
with swizzle_mode=[012] until we get a response on how to automatically detect.
2008-07-01 16:14:08 -07:00
Eric Anholt
e2baf564d1 [intel-gem] Bug #16326: Fix X tile unswizzling on 965.
Apparently a bit gets flipped in the addressing for some rows of each tile.
2008-06-17 11:18:02 -07:00
Keith Packard
537bbe6dec [intel-GEM] Add tiling support to swrast.
Accessing tiled surfaces without using the fence registers requires that
software deal with the address swizzling itself.
2008-05-06 10:51:08 -07:00
Xiang, Haihao
c30392f187 i965: fix segfault caused by commit e131c46b20. 2008-01-10 16:45:35 +08:00
Brian
ff73c783cc Simplify ctx->_NumColorDrawBuffers, _ColorDrawBuffers and fix bug 13835.
These fields are no longer indexed by shader output.  Now, we just have
a simple array of renderbuffer pointers.

If the shader writes to gl_FragData[i], send those colors to the N
_ColorDrawBuffers.  Otherwise, replicate the single gl_FragColor (or
the fixed-function color) to the N _ColorDrawBuffers.

A few more changes and simplifications can follow from this...
2008-01-06 10:43:20 -07:00
Eric Anholt
7c71ef3a3d [intel] Move bufmgr back to context instead of screen, fixing glthreads.
Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes.  It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965).  The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
2007-12-12 11:52:10 -08:00
Eric Anholt
77a5bcaff4 [intel] Move over files that will be shared with 965-fbo work. 2007-11-09 14:27:33 -08:00