When selecting an instruction to merge, we want to pre-remove that
instruction from the DAG, not the one we are merging it in, which
we had already pre-removed right before.
The reason this was not causing problems before is that the
consequence of this bug is we will choose the same instruction
again in the merge loop and trying to merge that instruction twice
will fail and we would break out of the merge loop and move on.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9304>
EXT_external_objects require we call glSignalSemaphoreEXT followed by a
glFlush. If the rendering workload is small when Signal and Flush
take place the relevant batch buffers with the actual rendering might
have been submitted already. In that case the following condition is met:
(iris_batch_bytes_used(batch) == 0). This causes:
glFlush() --> iris_fence_flush() -> iris_batch_flush() ->
_iris_batch_flush() to no-op, and so the fence doesn't get submitted to the
kernel. Then when anv tries to submit an execuf2 that must wait on the
shared VkSempahore / drm_syncobj fence, there isn't one and the kernel
rejects the batchbuffer causing an -EINVAL return of the execbuf2 ioctl
and a VK_DEVICE_LOST error. Empty batch buffers do have typically one
fence attached, but the ones carrying the extra fence from a
glSignalSempahore() call do have at least 2.
See also: the discussion in MR!4337.
v2: Changed the batch struct to have a contains_fence_signal variable
that is set to true when i915_EXEC_FENCE_SIGNAL fence is added to the
batch and off when batch is reset (Tapani Pälli)
Authored-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reported-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Tested-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Eleni Maria Stea <elene.mst@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8861>
The cache has been detangled from glsl and used outside it (with Vulkan drivers)
for years now.
This also cleans up the dependancies in the build file. The test doesn't
depend on the glsl lib but rather the util lib.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9327>
A recent commit stopped updating the inverse MVP matrix, because usually
only GLSL built-ins need it. However, TNL also needs it. So make sure
it's correct when needed.
Fixes: 10371c520c ("mesa: don't compute the ModelView * Projection matrix if not used")
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9346>
Fixes the following building error:
FAILED: out/target/product/x86_64/obj_x86/STATIC_LIBRARIES/libmesa_util_intermediates/xmlconfig.o
...
external/mesa/src/util/xmlconfig.c:1030:12: fatal error: 'driconf_static.h' file not found
^~~~~~~~~~~~~~~~~~
1 error generated.
Fixes: a6b0ceb ("driconf: Generate a static table when no xmlconfig")
Acked-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9294>
MR to move to python3 in Android build gen rules is still pending
The change is to avoid following building error:
FAILED: out/target/product/x86_64/gen/STATIC_LIBRARIES/libmesa_util_intermediates/driconf_static.h
/bin/bash -c "/usr/bin/python external/mesa/src/util/driconf_static.py external/mesa/src/util/00-mesa-defaults.conf > out/target/product/x86_64/gen/STATIC_LIBRARIES/libmesa_util_intermediates/driconf_static.h"
File "external/mesa/src/util/driconf_static.py", line 2
SyntaxError: Non-ASCII character '\xc2' in file external/mesa/src/util/driconf_static.py on line 2, but no encoding declared; see http://python.org/dev/peps/pep-0263/ for details
Fixes: a6b0ceb ("driconf: Generate a static table when no xmlconfig")
Acked-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9294>
A sequence like:
1) create sampler view CSO with UBWC resource
2) later create another sampler view or image view with the same
resource, but a format that triggers demoting the resource to
uncompressed
3) bind CSO created in step #1
would not work correctly, because the CSO created in step #1 is still
setup for UBWC, despite the fact that the resource had been demoted to
uncompressed.
Fortunately this is easy enough to detect, as the resource's seqno would
have been updated.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9321>
So far we were retrying the testing (through device rebooting) if we did
not detect the boot sequence.
But found a couple of times that the serial log can also be "lost"
during the testing process. In all those times a manual retry of the job
was enough to complete the test.
Thus, let's apply the retry once automatically in this case.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9335>
There are less copy instructions than sources, so instead of visiting each
source and rewriting it if it's uses a copy instruction, visit each copy
instruction and rewrite it's users.
Besides improving compile time, this also has a side effect of fixing a
rare situation where copy-propagation does not happen:
loop {
a = phi ..., b
c = vec ...
b = mov c.y
}
It might have been the case that a phi source could not be rewritten until
the copy was visited later.
Compile-time (nir_copy_prop):
Difference at 95.0% confidence
-2613.13 +/- 15.2094
-27.4333% +/- 0.150247%
(Student's t, pooled s = 17.963)
Comple-time (overall):
Difference at 95.0% confidence
-2627.89 +/- 201.557
-2.05404% +/- 0.156221%
(Student's t, pooled s = 238.048)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8784>
Midgard writeout arguments need to be written to in the same bundle the
writeout happens. Both csel, csel_v and their float variants also
require their conditional to be performed on the same bundle.
This patch prevents scheduling csel the same bundle as a writeout,
fixing the scheduling issue.
But... there's still room for optimizations since in some cases it might
be possible to fit all these instructions in the same bundle.
No shader-db changes.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9340>
We need to iterate the whole row, we can't be clever and only look at
one side, the symmetry doesn't work like that. See the original paper.
total instructions in shared programs: 69392 -> 69322 (-0.10%)
instructions in affected programs: 9002 -> 8932 (-0.78%)
helped: 82
HURT: 28
Instructions are helped.
total bundles in shared programs: 32225 -> 32155 (-0.22%)
bundles in affected programs: 4286 -> 4216 (-1.63%)
helped: 82
HURT: 28
Bundles are helped.
total quadwords in shared programs: 56102 -> 56102 (0.00%)
quadwords in affected programs: 0 -> 0
helped: 0
HURT: 0
total registers in shared programs: 4552 -> 4572 (0.44%)
registers in affected programs: 298 -> 318 (6.71%)
helped: 18
HURT: 38
Registers are HURT.
total threads in shared programs: 3772 -> 3775 (0.08%)
threads in affected programs: 84 -> 87 (3.57%)
helped: 15
HURT: 14
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 0 -> 0
spills in affected programs: 0 -> 0
helped: 0
HURT: 0
total fills in shared programs: 0 -> 0
fills in affected programs: 0 -> 0
helped: 0
HURT: 0
Fixes: 66ad64d73d ("pan/midgard: Implement linearly-constrained register allocation")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9338>
